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< #include "cpu/exec_context.hh"
---
> #include "cpu/thread_context.hh"
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< AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
---
> AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
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< if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
---
> if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
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< if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
---
> if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
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< int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
---
> int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
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< (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
---
> (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
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< AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
---
> AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
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< Addr pc = xc->readPC();
---
> Addr pc = tc->readPC();
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< (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
---
> (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
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< xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
---
> tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
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< if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
---
> if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
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< if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
---
> if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
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< int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
---
> int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));