tlb.cc (5568:d14250d688d2) tlb.cc (5569:baeee670d4ce)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 * Andrew Schultz
31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44
45using namespace std;
46
47namespace AlphaISA {
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 * Andrew Schultz
31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44
45using namespace std;
46
47namespace AlphaISA {
48
48///////////////////////////////////////////////////////////////////////
49//
50// Alpha TLB
51//
49///////////////////////////////////////////////////////////////////////
50//
51// Alpha TLB
52//
53
52#ifdef DEBUG
53bool uncacheBit39 = false;
54bool uncacheBit40 = false;
55#endif
56
54#ifdef DEBUG
55bool uncacheBit39 = false;
56bool uncacheBit40 = false;
57#endif
58
57#define MODE2MASK(X) (1 << (X))
59#define MODE2MASK(X) (1 << (X))
58
59TLB::TLB(const Params *p)
60 : BaseTLB(p), size(p->size), nlu(0)
61{
62 table = new TlbEntry[size];
63 memset(table, 0, sizeof(TlbEntry[size]));
64 flushCache();
65}
66
67TLB::~TLB()
68{
69 if (table)
70 delete [] table;
71}
72
73// look up an entry in the TLB
74TlbEntry *
75TLB::lookup(Addr vpn, uint8_t asn)
76{
77 // assume not found...
78 TlbEntry *retval = NULL;
79
80 if (EntryCache[0]) {
81 if (vpn == EntryCache[0]->tag &&
82 (EntryCache[0]->asma || EntryCache[0]->asn == asn))
83 retval = EntryCache[0];
84 else if (EntryCache[1]) {
85 if (vpn == EntryCache[1]->tag &&
86 (EntryCache[1]->asma || EntryCache[1]->asn == asn))
87 retval = EntryCache[1];
88 else if (EntryCache[2] && vpn == EntryCache[2]->tag &&
89 (EntryCache[2]->asma || EntryCache[2]->asn == asn))
90 retval = EntryCache[2];
91 }
92 }
93
94 if (retval == NULL) {
95 PageTable::const_iterator i = lookupTable.find(vpn);
96 if (i != lookupTable.end()) {
97 while (i->first == vpn) {
98 int index = i->second;
99 TlbEntry *entry = &table[index];
100 assert(entry->valid);
101 if (vpn == entry->tag && (entry->asma || entry->asn == asn)) {
102 retval = updateCache(entry);
103 break;
104 }
105
106 ++i;
107 }
108 }
109 }
110
111 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
112 retval ? "hit" : "miss", retval ? retval->ppn : 0);
113 return retval;
114}
115
60
61TLB::TLB(const Params *p)
62 : BaseTLB(p), size(p->size), nlu(0)
63{
64 table = new TlbEntry[size];
65 memset(table, 0, sizeof(TlbEntry[size]));
66 flushCache();
67}
68
69TLB::~TLB()
70{
71 if (table)
72 delete [] table;
73}
74
75// look up an entry in the TLB
76TlbEntry *
77TLB::lookup(Addr vpn, uint8_t asn)
78{
79 // assume not found...
80 TlbEntry *retval = NULL;
81
82 if (EntryCache[0]) {
83 if (vpn == EntryCache[0]->tag &&
84 (EntryCache[0]->asma || EntryCache[0]->asn == asn))
85 retval = EntryCache[0];
86 else if (EntryCache[1]) {
87 if (vpn == EntryCache[1]->tag &&
88 (EntryCache[1]->asma || EntryCache[1]->asn == asn))
89 retval = EntryCache[1];
90 else if (EntryCache[2] && vpn == EntryCache[2]->tag &&
91 (EntryCache[2]->asma || EntryCache[2]->asn == asn))
92 retval = EntryCache[2];
93 }
94 }
95
96 if (retval == NULL) {
97 PageTable::const_iterator i = lookupTable.find(vpn);
98 if (i != lookupTable.end()) {
99 while (i->first == vpn) {
100 int index = i->second;
101 TlbEntry *entry = &table[index];
102 assert(entry->valid);
103 if (vpn == entry->tag && (entry->asma || entry->asn == asn)) {
104 retval = updateCache(entry);
105 break;
106 }
107
108 ++i;
109 }
110 }
111 }
112
113 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
114 retval ? "hit" : "miss", retval ? retval->ppn : 0);
115 return retval;
116}
117
116
117Fault
118TLB::checkCacheability(RequestPtr &req, bool itb)
119{
118Fault
119TLB::checkCacheability(RequestPtr &req, bool itb)
120{
120// in Alpha, cacheability is controlled by upper-level bits of the
121// physical address
121 // in Alpha, cacheability is controlled by upper-level bits of the
122 // physical address
122
123
123/*
124 * We support having the uncacheable bit in either bit 39 or bit 40.
125 * The Turbolaser platform (and EV5) support having the bit in 39, but
126 * Tsunami (which Linux assumes uses an EV6) generates accesses with
127 * the bit in 40. So we must check for both, but we have debug flags
128 * to catch a weird case where both are used, which shouldn't happen.
129 */
124 /*
125 * We support having the uncacheable bit in either bit 39 or bit
126 * 40. The Turbolaser platform (and EV5) support having the bit
127 * in 39, but Tsunami (which Linux assumes uses an EV6) generates
128 * accesses with the bit in 40. So we must check for both, but we
129 * have debug flags to catch a weird case where both are used,
130 * which shouldn't happen.
131 */
130
131
132#if ALPHA_TLASER
133 if (req->getPaddr() & PAddrUncachedBit39)
134#else
135 if (req->getPaddr() & PAddrUncachedBit43)
136#endif
137 {
138 // IPR memory space not implemented
139 if (PAddrIprSpace(req->getPaddr())) {
140 return new UnimpFault("IPR memory space not implemented!");
141 } else {
142 // mark request as uncacheable
143 req->setFlags(req->getFlags() | UNCACHEABLE);
144
145#if !ALPHA_TLASER
132
133
134#if ALPHA_TLASER
135 if (req->getPaddr() & PAddrUncachedBit39)
136#else
137 if (req->getPaddr() & PAddrUncachedBit43)
138#endif
139 {
140 // IPR memory space not implemented
141 if (PAddrIprSpace(req->getPaddr())) {
142 return new UnimpFault("IPR memory space not implemented!");
143 } else {
144 // mark request as uncacheable
145 req->setFlags(req->getFlags() | UNCACHEABLE);
146
147#if !ALPHA_TLASER
146 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
148 // Clear bits 42:35 of the physical address (10-2 in
149 // Tsunami manual)
147 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
148#endif
149 }
150 // We shouldn't be able to read from an uncachable address in Alpha as
151 // we don't have a ROM and we don't want to try to fetch from a device
152 // register as we destroy any data that is clear-on-read.
153 if (req->isUncacheable() && itb)
154 return new UnimpFault("CPU trying to fetch from uncached I/O");
155
156 }
157 return NoFault;
158}
159
160
161// insert a new TLB entry
162void
163TLB::insert(Addr addr, TlbEntry &entry)
164{
165 flushCache();
166 VAddr vaddr = addr;
167 if (table[nlu].valid) {
168 Addr oldvpn = table[nlu].tag;
169 PageTable::iterator i = lookupTable.find(oldvpn);
170
171 if (i == lookupTable.end())
172 panic("TLB entry not found in lookupTable");
173
174 int index;
175 while ((index = i->second) != nlu) {
176 if (table[index].tag != oldvpn)
177 panic("TLB entry not found in lookupTable");
178
179 ++i;
180 }
181
182 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
183
184 lookupTable.erase(i);
185 }
186
187 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
188
189 table[nlu] = entry;
190 table[nlu].tag = vaddr.vpn();
191 table[nlu].valid = true;
192
193 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
194 nextnlu();
195}
196
197void
198TLB::flushAll()
199{
200 DPRINTF(TLB, "flushAll\n");
201 memset(table, 0, sizeof(TlbEntry[size]));
202 flushCache();
203 lookupTable.clear();
204 nlu = 0;
205}
206
207void
208TLB::flushProcesses()
209{
210 flushCache();
211 PageTable::iterator i = lookupTable.begin();
212 PageTable::iterator end = lookupTable.end();
213 while (i != end) {
214 int index = i->second;
215 TlbEntry *entry = &table[index];
216 assert(entry->valid);
217
218 // we can't increment i after we erase it, so save a copy and
219 // increment it to get the next entry now
220 PageTable::iterator cur = i;
221 ++i;
222
223 if (!entry->asma) {
150 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
151#endif
152 }
153 // We shouldn't be able to read from an uncachable address in Alpha as
154 // we don't have a ROM and we don't want to try to fetch from a device
155 // register as we destroy any data that is clear-on-read.
156 if (req->isUncacheable() && itb)
157 return new UnimpFault("CPU trying to fetch from uncached I/O");
158
159 }
160 return NoFault;
161}
162
163
164// insert a new TLB entry
165void
166TLB::insert(Addr addr, TlbEntry &entry)
167{
168 flushCache();
169 VAddr vaddr = addr;
170 if (table[nlu].valid) {
171 Addr oldvpn = table[nlu].tag;
172 PageTable::iterator i = lookupTable.find(oldvpn);
173
174 if (i == lookupTable.end())
175 panic("TLB entry not found in lookupTable");
176
177 int index;
178 while ((index = i->second) != nlu) {
179 if (table[index].tag != oldvpn)
180 panic("TLB entry not found in lookupTable");
181
182 ++i;
183 }
184
185 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
186
187 lookupTable.erase(i);
188 }
189
190 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
191
192 table[nlu] = entry;
193 table[nlu].tag = vaddr.vpn();
194 table[nlu].valid = true;
195
196 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
197 nextnlu();
198}
199
200void
201TLB::flushAll()
202{
203 DPRINTF(TLB, "flushAll\n");
204 memset(table, 0, sizeof(TlbEntry[size]));
205 flushCache();
206 lookupTable.clear();
207 nlu = 0;
208}
209
210void
211TLB::flushProcesses()
212{
213 flushCache();
214 PageTable::iterator i = lookupTable.begin();
215 PageTable::iterator end = lookupTable.end();
216 while (i != end) {
217 int index = i->second;
218 TlbEntry *entry = &table[index];
219 assert(entry->valid);
220
221 // we can't increment i after we erase it, so save a copy and
222 // increment it to get the next entry now
223 PageTable::iterator cur = i;
224 ++i;
225
226 if (!entry->asma) {
224 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn);
227 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index,
228 entry->tag, entry->ppn);
225 entry->valid = false;
226 lookupTable.erase(cur);
227 }
228 }
229}
230
231void
232TLB::flushAddr(Addr addr, uint8_t asn)
233{
234 flushCache();
235 VAddr vaddr = addr;
236
237 PageTable::iterator i = lookupTable.find(vaddr.vpn());
238 if (i == lookupTable.end())
239 return;
240
241 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
242 int index = i->second;
243 TlbEntry *entry = &table[index];
244 assert(entry->valid);
245
246 if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
247 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
248 entry->ppn);
249
250 // invalidate this entry
251 entry->valid = false;
252
253 lookupTable.erase(i++);
254 } else {
255 ++i;
256 }
257 }
258}
259
260
261void
262TLB::serialize(ostream &os)
263{
264 SERIALIZE_SCALAR(size);
265 SERIALIZE_SCALAR(nlu);
266
267 for (int i = 0; i < size; i++) {
268 nameOut(os, csprintf("%s.Entry%d", name(), i));
269 table[i].serialize(os);
270 }
271}
272
273void
274TLB::unserialize(Checkpoint *cp, const string &section)
275{
276 UNSERIALIZE_SCALAR(size);
277 UNSERIALIZE_SCALAR(nlu);
278
279 for (int i = 0; i < size; i++) {
280 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
281 if (table[i].valid) {
282 lookupTable.insert(make_pair(table[i].tag, i));
283 }
284 }
285}
286
229 entry->valid = false;
230 lookupTable.erase(cur);
231 }
232 }
233}
234
235void
236TLB::flushAddr(Addr addr, uint8_t asn)
237{
238 flushCache();
239 VAddr vaddr = addr;
240
241 PageTable::iterator i = lookupTable.find(vaddr.vpn());
242 if (i == lookupTable.end())
243 return;
244
245 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
246 int index = i->second;
247 TlbEntry *entry = &table[index];
248 assert(entry->valid);
249
250 if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
251 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
252 entry->ppn);
253
254 // invalidate this entry
255 entry->valid = false;
256
257 lookupTable.erase(i++);
258 } else {
259 ++i;
260 }
261 }
262}
263
264
265void
266TLB::serialize(ostream &os)
267{
268 SERIALIZE_SCALAR(size);
269 SERIALIZE_SCALAR(nlu);
270
271 for (int i = 0; i < size; i++) {
272 nameOut(os, csprintf("%s.Entry%d", name(), i));
273 table[i].serialize(os);
274 }
275}
276
277void
278TLB::unserialize(Checkpoint *cp, const string &section)
279{
280 UNSERIALIZE_SCALAR(size);
281 UNSERIALIZE_SCALAR(nlu);
282
283 for (int i = 0; i < size; i++) {
284 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
285 if (table[i].valid) {
286 lookupTable.insert(make_pair(table[i].tag, i));
287 }
288 }
289}
290
287
288///////////////////////////////////////////////////////////////////////
289//
290// Alpha ITB
291//
292ITB::ITB(const Params *p)
293 : TLB(p)
294{}
295
296
297void
298ITB::regStats()
299{
300 hits
301 .name(name() + ".hits")
302 .desc("ITB hits");
303 misses
304 .name(name() + ".misses")
305 .desc("ITB misses");
306 acv
307 .name(name() + ".acv")
308 .desc("ITB acv");
309 accesses
310 .name(name() + ".accesses")
311 .desc("ITB accesses");
312
313 accesses = hits + misses;
314}
315
291///////////////////////////////////////////////////////////////////////
292//
293// Alpha ITB
294//
295ITB::ITB(const Params *p)
296 : TLB(p)
297{}
298
299
300void
301ITB::regStats()
302{
303 hits
304 .name(name() + ".hits")
305 .desc("ITB hits");
306 misses
307 .name(name() + ".misses")
308 .desc("ITB misses");
309 acv
310 .name(name() + ".acv")
311 .desc("ITB acv");
312 accesses
313 .name(name() + ".accesses")
314 .desc("ITB accesses");
315
316 accesses = hits + misses;
317}
318
316
317Fault
318ITB::translate(RequestPtr &req, ThreadContext *tc)
319{
320 //If this is a pal pc, then set PHYSICAL
319Fault
320ITB::translate(RequestPtr &req, ThreadContext *tc)
321{
322 //If this is a pal pc, then set PHYSICAL
321 if(FULL_SYSTEM && PcPAL(req->getPC()))
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
322 req->setFlags(req->getFlags() | PHYSICAL);
323
324 if (PcPAL(req->getPC())) {
325 // strip off PAL PC marker (lsb is 1)
326 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
327 hits++;
328 return NoFault;
329 }
330
331 if (req->getFlags() & PHYSICAL) {
332 req->setPaddr(req->getVaddr());
333 } else {
334 // verify that this is a good virtual address
335 if (!validVirtualAddress(req->getVaddr())) {
336 acv++;
337 return new ItbAcvFault(req->getVaddr());
338 }
339
340
341 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
342 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
343#if ALPHA_TLASER
344 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
345 VAddrSpaceEV5(req->getVaddr()) == 2)
346#else
347 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
348#endif
349 {
350 // only valid in kernel mode
351 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
352 mode_kernel) {
353 acv++;
354 return new ItbAcvFault(req->getVaddr());
355 }
356
357 req->setPaddr(req->getVaddr() & PAddrImplMask);
358
359#if !ALPHA_TLASER
360 // sign extend the physical address properly
361 if (req->getPaddr() & PAddrUncachedBit40)
362 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
363 else
364 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
365#endif
366
367 } else {
368 // not a physical address: need to look up pte
369 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
370 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
371 asn);
372
373 if (!entry) {
374 misses++;
375 return new ItbPageFault(req->getVaddr());
376 }
377
378 req->setPaddr((entry->ppn << PageShift) +
379 (VAddr(req->getVaddr()).offset()
380 & ~3));
381
382 // check permissions for this access
383 if (!(entry->xre &
384 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
385 // instruction access fault
386 acv++;
387 return new ItbAcvFault(req->getVaddr());
388 }
389
390 hits++;
391 }
392 }
393
394 // check that the physical address is ok (catch bad physical addresses)
395 if (req->getPaddr() & ~PAddrImplMask)
396 return genMachineCheckFault();
397
398 return checkCacheability(req, true);
399
400}
401
402///////////////////////////////////////////////////////////////////////
403//
404// Alpha DTB
405//
324 req->setFlags(req->getFlags() | PHYSICAL);
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
329 hits++;
330 return NoFault;
331 }
332
333 if (req->getFlags() & PHYSICAL) {
334 req->setPaddr(req->getVaddr());
335 } else {
336 // verify that this is a good virtual address
337 if (!validVirtualAddress(req->getVaddr())) {
338 acv++;
339 return new ItbAcvFault(req->getVaddr());
340 }
341
342
343 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
344 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
345#if ALPHA_TLASER
346 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
347 VAddrSpaceEV5(req->getVaddr()) == 2)
348#else
349 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
350#endif
351 {
352 // only valid in kernel mode
353 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
354 mode_kernel) {
355 acv++;
356 return new ItbAcvFault(req->getVaddr());
357 }
358
359 req->setPaddr(req->getVaddr() & PAddrImplMask);
360
361#if !ALPHA_TLASER
362 // sign extend the physical address properly
363 if (req->getPaddr() & PAddrUncachedBit40)
364 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
365 else
366 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
367#endif
368
369 } else {
370 // not a physical address: need to look up pte
371 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
372 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
373 asn);
374
375 if (!entry) {
376 misses++;
377 return new ItbPageFault(req->getVaddr());
378 }
379
380 req->setPaddr((entry->ppn << PageShift) +
381 (VAddr(req->getVaddr()).offset()
382 & ~3));
383
384 // check permissions for this access
385 if (!(entry->xre &
386 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
387 // instruction access fault
388 acv++;
389 return new ItbAcvFault(req->getVaddr());
390 }
391
392 hits++;
393 }
394 }
395
396 // check that the physical address is ok (catch bad physical addresses)
397 if (req->getPaddr() & ~PAddrImplMask)
398 return genMachineCheckFault();
399
400 return checkCacheability(req, true);
401
402}
403
404///////////////////////////////////////////////////////////////////////
405//
406// Alpha DTB
407//
406 DTB::DTB(const Params *p)
408DTB::DTB(const Params *p)
407 : TLB(p)
408{}
409
410void
411DTB::regStats()
412{
413 read_hits
414 .name(name() + ".read_hits")
415 .desc("DTB read hits")
416 ;
417
418 read_misses
419 .name(name() + ".read_misses")
420 .desc("DTB read misses")
421 ;
422
423 read_acv
424 .name(name() + ".read_acv")
425 .desc("DTB read access violations")
426 ;
427
428 read_accesses
429 .name(name() + ".read_accesses")
430 .desc("DTB read accesses")
431 ;
432
433 write_hits
434 .name(name() + ".write_hits")
435 .desc("DTB write hits")
436 ;
437
438 write_misses
439 .name(name() + ".write_misses")
440 .desc("DTB write misses")
441 ;
442
443 write_acv
444 .name(name() + ".write_acv")
445 .desc("DTB write access violations")
446 ;
447
448 write_accesses
449 .name(name() + ".write_accesses")
450 .desc("DTB write accesses")
451 ;
452
453 hits
454 .name(name() + ".hits")
455 .desc("DTB hits")
456 ;
457
458 misses
459 .name(name() + ".misses")
460 .desc("DTB misses")
461 ;
462
463 acv
464 .name(name() + ".acv")
465 .desc("DTB access violations")
466 ;
467
468 accesses
469 .name(name() + ".accesses")
470 .desc("DTB accesses")
471 ;
472
473 hits = read_hits + write_hits;
474 misses = read_misses + write_misses;
475 acv = read_acv + write_acv;
476 accesses = read_accesses + write_accesses;
477}
478
479Fault
480DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
481{
482 Addr pc = tc->readPC();
483
484 mode_type mode =
485 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
486
409 : TLB(p)
410{}
411
412void
413DTB::regStats()
414{
415 read_hits
416 .name(name() + ".read_hits")
417 .desc("DTB read hits")
418 ;
419
420 read_misses
421 .name(name() + ".read_misses")
422 .desc("DTB read misses")
423 ;
424
425 read_acv
426 .name(name() + ".read_acv")
427 .desc("DTB read access violations")
428 ;
429
430 read_accesses
431 .name(name() + ".read_accesses")
432 .desc("DTB read accesses")
433 ;
434
435 write_hits
436 .name(name() + ".write_hits")
437 .desc("DTB write hits")
438 ;
439
440 write_misses
441 .name(name() + ".write_misses")
442 .desc("DTB write misses")
443 ;
444
445 write_acv
446 .name(name() + ".write_acv")
447 .desc("DTB write access violations")
448 ;
449
450 write_accesses
451 .name(name() + ".write_accesses")
452 .desc("DTB write accesses")
453 ;
454
455 hits
456 .name(name() + ".hits")
457 .desc("DTB hits")
458 ;
459
460 misses
461 .name(name() + ".misses")
462 .desc("DTB misses")
463 ;
464
465 acv
466 .name(name() + ".acv")
467 .desc("DTB access violations")
468 ;
469
470 accesses
471 .name(name() + ".accesses")
472 .desc("DTB accesses")
473 ;
474
475 hits = read_hits + write_hits;
476 misses = read_misses + write_misses;
477 acv = read_acv + write_acv;
478 accesses = read_accesses + write_accesses;
479}
480
481Fault
482DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
483{
484 Addr pc = tc->readPC();
485
486 mode_type mode =
487 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
488
487
488 /**
489 * Check for alignment faults
490 */
491 if (req->getVaddr() & (req->getSize() - 1)) {
492 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
493 req->getSize());
494 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
495 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
496 }
497
498 if (PcPAL(pc)) {
499 mode = (req->getFlags() & ALTMODE) ?
500 (mode_type)ALT_MODE_AM(
501 tc->readMiscRegNoEffect(IPR_ALT_MODE))
502 : mode_kernel;
503 }
504
505 if (req->getFlags() & PHYSICAL) {
506 req->setPaddr(req->getVaddr());
507 } else {
508 // verify that this is a good virtual address
509 if (!validVirtualAddress(req->getVaddr())) {
510 if (write) { write_acv++; } else { read_acv++; }
511 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
512 MM_STAT_BAD_VA_MASK |
513 MM_STAT_ACV_MASK;
514 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
515 }
516
517 // Check for "superpage" mapping
518#if ALPHA_TLASER
519 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
520 VAddrSpaceEV5(req->getVaddr()) == 2)
521#else
522 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
523#endif
524 {
489 /**
490 * Check for alignment faults
491 */
492 if (req->getVaddr() & (req->getSize() - 1)) {
493 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
494 req->getSize());
495 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
496 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
497 }
498
499 if (PcPAL(pc)) {
500 mode = (req->getFlags() & ALTMODE) ?
501 (mode_type)ALT_MODE_AM(
502 tc->readMiscRegNoEffect(IPR_ALT_MODE))
503 : mode_kernel;
504 }
505
506 if (req->getFlags() & PHYSICAL) {
507 req->setPaddr(req->getVaddr());
508 } else {
509 // verify that this is a good virtual address
510 if (!validVirtualAddress(req->getVaddr())) {
511 if (write) { write_acv++; } else { read_acv++; }
512 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
513 MM_STAT_BAD_VA_MASK |
514 MM_STAT_ACV_MASK;
515 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
516 }
517
518 // Check for "superpage" mapping
519#if ALPHA_TLASER
520 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
521 VAddrSpaceEV5(req->getVaddr()) == 2)
522#else
523 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
524#endif
525 {
525
526 // only valid in kernel mode
527 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
528 mode_kernel) {
529 if (write) { write_acv++; } else { read_acv++; }
530 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
531 MM_STAT_ACV_MASK);
526 // only valid in kernel mode
527 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
528 mode_kernel) {
529 if (write) { write_acv++; } else { read_acv++; }
530 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
531 MM_STAT_ACV_MASK);
532 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
532
533 return new DtbAcvFault(req->getVaddr(), req->getFlags(),
534 flags);
533 }
534
535 req->setPaddr(req->getVaddr() & PAddrImplMask);
536
537#if !ALPHA_TLASER
538 // sign extend the physical address properly
539 if (req->getPaddr() & PAddrUncachedBit40)
540 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
541 else
542 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
543#endif
544
545 } else {
546 if (write)
547 write_accesses++;
548 else
549 read_accesses++;
550
551 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
552
553 // not a physical address: need to look up pte
554 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
555
556 if (!entry) {
557 // page fault
558 if (write) { write_misses++; } else { read_misses++; }
559 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
560 MM_STAT_DTB_MISS_MASK;
561 return (req->getFlags() & VPTE) ?
562 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
563 flags)) :
564 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
565 flags));
566 }
567
568 req->setPaddr((entry->ppn << PageShift) +
569 VAddr(req->getVaddr()).offset());
570
571 if (write) {
572 if (!(entry->xwe & MODE2MASK(mode))) {
573 // declare the instruction access fault
574 write_acv++;
575 uint64_t flags = MM_STAT_WR_MASK |
576 MM_STAT_ACV_MASK |
577 (entry->fonw ? MM_STAT_FONW_MASK : 0);
535 }
536
537 req->setPaddr(req->getVaddr() & PAddrImplMask);
538
539#if !ALPHA_TLASER
540 // sign extend the physical address properly
541 if (req->getPaddr() & PAddrUncachedBit40)
542 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
543 else
544 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
545#endif
546
547 } else {
548 if (write)
549 write_accesses++;
550 else
551 read_accesses++;
552
553 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
554
555 // not a physical address: need to look up pte
556 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
557
558 if (!entry) {
559 // page fault
560 if (write) { write_misses++; } else { read_misses++; }
561 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
562 MM_STAT_DTB_MISS_MASK;
563 return (req->getFlags() & VPTE) ?
564 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
565 flags)) :
566 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
567 flags));
568 }
569
570 req->setPaddr((entry->ppn << PageShift) +
571 VAddr(req->getVaddr()).offset());
572
573 if (write) {
574 if (!(entry->xwe & MODE2MASK(mode))) {
575 // declare the instruction access fault
576 write_acv++;
577 uint64_t flags = MM_STAT_WR_MASK |
578 MM_STAT_ACV_MASK |
579 (entry->fonw ? MM_STAT_FONW_MASK : 0);
578 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
580 return new DtbPageFault(req->getVaddr(), req->getFlags(),
581 flags);
579 }
580 if (entry->fonw) {
581 write_acv++;
582 }
583 if (entry->fonw) {
584 write_acv++;
582 uint64_t flags = MM_STAT_WR_MASK |
583 MM_STAT_FONW_MASK;
584 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
585 uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
586 return new DtbPageFault(req->getVaddr(), req->getFlags(),
587 flags);
585 }
586 } else {
587 if (!(entry->xre & MODE2MASK(mode))) {
588 read_acv++;
589 uint64_t flags = MM_STAT_ACV_MASK |
590 (entry->fonr ? MM_STAT_FONR_MASK : 0);
588 }
589 } else {
590 if (!(entry->xre & MODE2MASK(mode))) {
591 read_acv++;
592 uint64_t flags = MM_STAT_ACV_MASK |
593 (entry->fonr ? MM_STAT_FONR_MASK : 0);
591 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
594 return new DtbAcvFault(req->getVaddr(), req->getFlags(),
595 flags);
592 }
593 if (entry->fonr) {
594 read_acv++;
595 uint64_t flags = MM_STAT_FONR_MASK;
596 }
597 if (entry->fonr) {
598 read_acv++;
599 uint64_t flags = MM_STAT_FONR_MASK;
596 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
600 return new DtbPageFault(req->getVaddr(), req->getFlags(),
601 flags);
597 }
598 }
599 }
600
601 if (write)
602 write_hits++;
603 else
604 read_hits++;
605 }
606
607 // check that the physical address is ok (catch bad physical addresses)
608 if (req->getPaddr() & ~PAddrImplMask)
609 return genMachineCheckFault();
610
611 return checkCacheability(req);
612}
613
614TlbEntry &
615TLB::index(bool advance)
616{
617 TlbEntry *entry = &table[nlu];
618
619 if (advance)
620 nextnlu();
621
622 return *entry;
623}
624
602 }
603 }
604 }
605
606 if (write)
607 write_hits++;
608 else
609 read_hits++;
610 }
611
612 // check that the physical address is ok (catch bad physical addresses)
613 if (req->getPaddr() & ~PAddrImplMask)
614 return genMachineCheckFault();
615
616 return checkCacheability(req);
617}
618
619TlbEntry &
620TLB::index(bool advance)
621{
622 TlbEntry *entry = &table[nlu];
623
624 if (advance)
625 nextnlu();
626
627 return *entry;
628}
629
625} // namespace AlphaISA
630/* end namespace AlphaISA */ }
626
627AlphaISA::ITB *
628AlphaITBParams::create()
629{
630 return new AlphaISA::ITB(this);
631}
632
633AlphaISA::DTB *
634AlphaDTBParams::create()
635{
636 return new AlphaISA::DTB(this);
637}
631
632AlphaISA::ITB *
633AlphaITBParams::create()
634{
635 return new AlphaISA::ITB(this);
636}
637
638AlphaISA::DTB *
639AlphaDTBParams::create()
640{
641 return new AlphaISA::DTB(this);
642}