1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 * Andrew Schultz
31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46
47using namespace std;
48using namespace EV5;
49
50namespace AlphaISA {
51///////////////////////////////////////////////////////////////////////
52//
53// Alpha TLB
54//
55#ifdef DEBUG
56bool uncacheBit39 = false;
57bool uncacheBit40 = false;
58#endif
59
60#define MODE2MASK(X) (1 << (X))
61
62TLB::TLB(const string &name, int s)
63 : SimObject(name), size(s), nlu(0)
64{
65 table = new PTE[size];
66 memset(table, 0, sizeof(PTE[size]));
67 flushCache();
68}
69
70TLB::~TLB()
71{
72 if (table)
73 delete [] table;
74}
75
76// look up an entry in the TLB
77PTE *
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 * Andrew Schultz
31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46
47using namespace std;
48using namespace EV5;
49
50namespace AlphaISA {
51///////////////////////////////////////////////////////////////////////
52//
53// Alpha TLB
54//
55#ifdef DEBUG
56bool uncacheBit39 = false;
57bool uncacheBit40 = false;
58#endif
59
60#define MODE2MASK(X) (1 << (X))
61
62TLB::TLB(const string &name, int s)
63 : SimObject(name), size(s), nlu(0)
64{
65 table = new PTE[size];
66 memset(table, 0, sizeof(PTE[size]));
67 flushCache();
68}
69
70TLB::~TLB()
71{
72 if (table)
73 delete [] table;
74}
75
76// look up an entry in the TLB
77PTE *
|
78TLB::lookup(Addr vpn, uint8_t asn) const
| 78TLB::lookup(Addr vpn, uint8_t asn)
|
79{
80 // assume not found...
81 PTE *retval = NULL;
82
83 if (PTECache[0]) {
84 if (vpn == PTECache[0]->tag &&
85 (PTECache[0]->asma || PTECache[0]->asn == asn))
86 retval = PTECache[0];
87 else if (PTECache[1]) {
88 if (vpn == PTECache[1]->tag &&
89 (PTECache[1]->asma || PTECache[1]->asn == asn))
90 retval = PTECache[1];
91 else if (PTECache[2] && vpn == PTECache[2]->tag &&
92 (PTECache[2]->asma || PTECache[2]->asn == asn))
93 retval = PTECache[2];
94 }
95 }
96
| 79{
80 // assume not found...
81 PTE *retval = NULL;
82
83 if (PTECache[0]) {
84 if (vpn == PTECache[0]->tag &&
85 (PTECache[0]->asma || PTECache[0]->asn == asn))
86 retval = PTECache[0];
87 else if (PTECache[1]) {
88 if (vpn == PTECache[1]->tag &&
89 (PTECache[1]->asma || PTECache[1]->asn == asn))
90 retval = PTECache[1];
91 else if (PTECache[2] && vpn == PTECache[2]->tag &&
92 (PTECache[2]->asma || PTECache[2]->asn == asn))
93 retval = PTECache[2];
94 }
95 }
96
|
97 if (retval == NULL)
| 97 if (retval == NULL) {
|
98 PageTable::const_iterator i = lookupTable.find(vpn);
99 if (i != lookupTable.end()) {
100 while (i->first == vpn) {
101 int index = i->second;
102 PTE *pte = &table[index];
103 assert(pte->valid);
104 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
| 98 PageTable::const_iterator i = lookupTable.find(vpn);
99 if (i != lookupTable.end()) {
100 while (i->first == vpn) {
101 int index = i->second;
102 PTE *pte = &table[index];
103 assert(pte->valid);
104 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
|
105 retval = pte;
106 PTECache[2] = PTECache[1];
107 PTECache[1] = PTECache[0];
108 PTECache[0] = pte;
| 105 retval = updateCache(pte);
|
109 break;
110 }
111
112 ++i;
113 }
114 }
115 }
116
117 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
118 retval ? "hit" : "miss", retval ? retval->ppn : 0);
119 return retval;
120}
121
122
123Fault
124TLB::checkCacheability(RequestPtr &req)
125{
126// in Alpha, cacheability is controlled by upper-level bits of the
127// physical address
128
129/*
130 * We support having the uncacheable bit in either bit 39 or bit 40.
131 * The Turbolaser platform (and EV5) support having the bit in 39, but
132 * Tsunami (which Linux assumes uses an EV6) generates accesses with
133 * the bit in 40. So we must check for both, but we have debug flags
134 * to catch a weird case where both are used, which shouldn't happen.
135 */
136
137
138#if ALPHA_TLASER
139 if (req->getPaddr() & PAddrUncachedBit39)
140#else
141 if (req->getPaddr() & PAddrUncachedBit43)
142#endif
143 {
144 // IPR memory space not implemented
145 if (PAddrIprSpace(req->getPaddr())) {
146 return new UnimpFault("IPR memory space not implemented!");
147 } else {
148 // mark request as uncacheable
149 req->setFlags(req->getFlags() | UNCACHEABLE);
150
151#if !ALPHA_TLASER
152 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
153 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
154#endif
155 }
156 }
157 return NoFault;
158}
159
160
161// insert a new TLB entry
162void
163TLB::insert(Addr addr, PTE &pte)
164{
165 flushCache();
166 VAddr vaddr = addr;
167 if (table[nlu].valid) {
168 Addr oldvpn = table[nlu].tag;
169 PageTable::iterator i = lookupTable.find(oldvpn);
170
171 if (i == lookupTable.end())
172 panic("TLB entry not found in lookupTable");
173
174 int index;
175 while ((index = i->second) != nlu) {
176 if (table[index].tag != oldvpn)
177 panic("TLB entry not found in lookupTable");
178
179 ++i;
180 }
181
182 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
183
184 lookupTable.erase(i);
185 }
186
187 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
188
189 table[nlu] = pte;
190 table[nlu].tag = vaddr.vpn();
191 table[nlu].valid = true;
192
193 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
194 nextnlu();
195}
196
197void
198TLB::flushAll()
199{
200 DPRINTF(TLB, "flushAll\n");
201 memset(table, 0, sizeof(PTE[size]));
202 flushCache();
203 lookupTable.clear();
204 nlu = 0;
205}
206
207void
208TLB::flushProcesses()
209{
210 flushCache();
211 PageTable::iterator i = lookupTable.begin();
212 PageTable::iterator end = lookupTable.end();
213 while (i != end) {
214 int index = i->second;
215 PTE *pte = &table[index];
216 assert(pte->valid);
217
218 // we can't increment i after we erase it, so save a copy and
219 // increment it to get the next entry now
220 PageTable::iterator cur = i;
221 ++i;
222
223 if (!pte->asma) {
224 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
225 pte->valid = false;
226 lookupTable.erase(cur);
227 }
228 }
229}
230
231void
232TLB::flushAddr(Addr addr, uint8_t asn)
233{
234 flushCache();
235 VAddr vaddr = addr;
236
237 PageTable::iterator i = lookupTable.find(vaddr.vpn());
238 if (i == lookupTable.end())
239 return;
240
241 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
242 int index = i->second;
243 PTE *pte = &table[index];
244 assert(pte->valid);
245
246 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
247 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
248 pte->ppn);
249
250 // invalidate this entry
251 pte->valid = false;
252
253 lookupTable.erase(i++);
254 } else {
255 ++i;
256 }
257 }
258}
259
260
261void
262TLB::serialize(ostream &os)
263{
264 SERIALIZE_SCALAR(size);
265 SERIALIZE_SCALAR(nlu);
266
267 for (int i = 0; i < size; i++) {
268 nameOut(os, csprintf("%s.PTE%d", name(), i));
269 table[i].serialize(os);
270 }
271}
272
273void
274TLB::unserialize(Checkpoint *cp, const string §ion)
275{
276 UNSERIALIZE_SCALAR(size);
277 UNSERIALIZE_SCALAR(nlu);
278
279 for (int i = 0; i < size; i++) {
280 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
281 if (table[i].valid) {
282 lookupTable.insert(make_pair(table[i].tag, i));
283 }
284 }
285}
286
287
288///////////////////////////////////////////////////////////////////////
289//
290// Alpha ITB
291//
292ITB::ITB(const std::string &name, int size)
293 : TLB(name, size)
294{}
295
296
297void
298ITB::regStats()
299{
300 hits
301 .name(name() + ".hits")
302 .desc("ITB hits");
303 misses
304 .name(name() + ".misses")
305 .desc("ITB misses");
306 acv
307 .name(name() + ".acv")
308 .desc("ITB acv");
309 accesses
310 .name(name() + ".accesses")
311 .desc("ITB accesses");
312
313 accesses = hits + misses;
314}
315
316
317Fault
| 106 break;
107 }
108
109 ++i;
110 }
111 }
112 }
113
114 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
115 retval ? "hit" : "miss", retval ? retval->ppn : 0);
116 return retval;
117}
118
119
120Fault
121TLB::checkCacheability(RequestPtr &req)
122{
123// in Alpha, cacheability is controlled by upper-level bits of the
124// physical address
125
126/*
127 * We support having the uncacheable bit in either bit 39 or bit 40.
128 * The Turbolaser platform (and EV5) support having the bit in 39, but
129 * Tsunami (which Linux assumes uses an EV6) generates accesses with
130 * the bit in 40. So we must check for both, but we have debug flags
131 * to catch a weird case where both are used, which shouldn't happen.
132 */
133
134
135#if ALPHA_TLASER
136 if (req->getPaddr() & PAddrUncachedBit39)
137#else
138 if (req->getPaddr() & PAddrUncachedBit43)
139#endif
140 {
141 // IPR memory space not implemented
142 if (PAddrIprSpace(req->getPaddr())) {
143 return new UnimpFault("IPR memory space not implemented!");
144 } else {
145 // mark request as uncacheable
146 req->setFlags(req->getFlags() | UNCACHEABLE);
147
148#if !ALPHA_TLASER
149 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
150 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
151#endif
152 }
153 }
154 return NoFault;
155}
156
157
158// insert a new TLB entry
159void
160TLB::insert(Addr addr, PTE &pte)
161{
162 flushCache();
163 VAddr vaddr = addr;
164 if (table[nlu].valid) {
165 Addr oldvpn = table[nlu].tag;
166 PageTable::iterator i = lookupTable.find(oldvpn);
167
168 if (i == lookupTable.end())
169 panic("TLB entry not found in lookupTable");
170
171 int index;
172 while ((index = i->second) != nlu) {
173 if (table[index].tag != oldvpn)
174 panic("TLB entry not found in lookupTable");
175
176 ++i;
177 }
178
179 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
180
181 lookupTable.erase(i);
182 }
183
184 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
185
186 table[nlu] = pte;
187 table[nlu].tag = vaddr.vpn();
188 table[nlu].valid = true;
189
190 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
191 nextnlu();
192}
193
194void
195TLB::flushAll()
196{
197 DPRINTF(TLB, "flushAll\n");
198 memset(table, 0, sizeof(PTE[size]));
199 flushCache();
200 lookupTable.clear();
201 nlu = 0;
202}
203
204void
205TLB::flushProcesses()
206{
207 flushCache();
208 PageTable::iterator i = lookupTable.begin();
209 PageTable::iterator end = lookupTable.end();
210 while (i != end) {
211 int index = i->second;
212 PTE *pte = &table[index];
213 assert(pte->valid);
214
215 // we can't increment i after we erase it, so save a copy and
216 // increment it to get the next entry now
217 PageTable::iterator cur = i;
218 ++i;
219
220 if (!pte->asma) {
221 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
222 pte->valid = false;
223 lookupTable.erase(cur);
224 }
225 }
226}
227
228void
229TLB::flushAddr(Addr addr, uint8_t asn)
230{
231 flushCache();
232 VAddr vaddr = addr;
233
234 PageTable::iterator i = lookupTable.find(vaddr.vpn());
235 if (i == lookupTable.end())
236 return;
237
238 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
239 int index = i->second;
240 PTE *pte = &table[index];
241 assert(pte->valid);
242
243 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
244 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
245 pte->ppn);
246
247 // invalidate this entry
248 pte->valid = false;
249
250 lookupTable.erase(i++);
251 } else {
252 ++i;
253 }
254 }
255}
256
257
258void
259TLB::serialize(ostream &os)
260{
261 SERIALIZE_SCALAR(size);
262 SERIALIZE_SCALAR(nlu);
263
264 for (int i = 0; i < size; i++) {
265 nameOut(os, csprintf("%s.PTE%d", name(), i));
266 table[i].serialize(os);
267 }
268}
269
270void
271TLB::unserialize(Checkpoint *cp, const string §ion)
272{
273 UNSERIALIZE_SCALAR(size);
274 UNSERIALIZE_SCALAR(nlu);
275
276 for (int i = 0; i < size; i++) {
277 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
278 if (table[i].valid) {
279 lookupTable.insert(make_pair(table[i].tag, i));
280 }
281 }
282}
283
284
285///////////////////////////////////////////////////////////////////////
286//
287// Alpha ITB
288//
289ITB::ITB(const std::string &name, int size)
290 : TLB(name, size)
291{}
292
293
294void
295ITB::regStats()
296{
297 hits
298 .name(name() + ".hits")
299 .desc("ITB hits");
300 misses
301 .name(name() + ".misses")
302 .desc("ITB misses");
303 acv
304 .name(name() + ".acv")
305 .desc("ITB acv");
306 accesses
307 .name(name() + ".accesses")
308 .desc("ITB accesses");
309
310 accesses = hits + misses;
311}
312
313
314Fault
|
318ITB::translate(RequestPtr &req, ThreadContext *tc) const
| 315ITB::translate(RequestPtr &req, ThreadContext *tc)
|
319{
320 //If this is a pal pc, then set PHYSICAL
321 if(FULL_SYSTEM && PcPAL(req->getPC()))
322 req->setFlags(req->getFlags() | PHYSICAL);
323
324 if (PcPAL(req->getPC())) {
325 // strip off PAL PC marker (lsb is 1)
326 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
327 hits++;
328 return NoFault;
329 }
330
331 if (req->getFlags() & PHYSICAL) {
332 req->setPaddr(req->getVaddr());
333 } else {
334 // verify that this is a good virtual address
335 if (!validVirtualAddress(req->getVaddr())) {
336 acv++;
337 return new ItbAcvFault(req->getVaddr());
338 }
339
340
341 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
342 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
343#if ALPHA_TLASER
344 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
345 VAddrSpaceEV5(req->getVaddr()) == 2)
346#else
347 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
348#endif
349 {
350 // only valid in kernel mode
351 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
352 mode_kernel) {
353 acv++;
354 return new ItbAcvFault(req->getVaddr());
355 }
356
357 req->setPaddr(req->getVaddr() & PAddrImplMask);
358
359#if !ALPHA_TLASER
360 // sign extend the physical address properly
361 if (req->getPaddr() & PAddrUncachedBit40)
362 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
363 else
364 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
365#endif
366
367 } else {
368 // not a physical address: need to look up pte
369 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
370 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
371 asn);
372
373 if (!pte) {
374 misses++;
375 return new ItbPageFault(req->getVaddr());
376 }
377
378 req->setPaddr((pte->ppn << PageShift) +
379 (VAddr(req->getVaddr()).offset()
380 & ~3));
381
382 // check permissions for this access
383 if (!(pte->xre &
384 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
385 // instruction access fault
386 acv++;
387 return new ItbAcvFault(req->getVaddr());
388 }
389
390 hits++;
391 }
392 }
393
394 // check that the physical address is ok (catch bad physical addresses)
395 if (req->getPaddr() & ~PAddrImplMask)
396 return genMachineCheckFault();
397
398 return checkCacheability(req);
399
400}
401
402///////////////////////////////////////////////////////////////////////
403//
404// Alpha DTB
405//
406 DTB::DTB(const std::string &name, int size)
407 : TLB(name, size)
408{}
409
410void
411DTB::regStats()
412{
413 read_hits
414 .name(name() + ".read_hits")
415 .desc("DTB read hits")
416 ;
417
418 read_misses
419 .name(name() + ".read_misses")
420 .desc("DTB read misses")
421 ;
422
423 read_acv
424 .name(name() + ".read_acv")
425 .desc("DTB read access violations")
426 ;
427
428 read_accesses
429 .name(name() + ".read_accesses")
430 .desc("DTB read accesses")
431 ;
432
433 write_hits
434 .name(name() + ".write_hits")
435 .desc("DTB write hits")
436 ;
437
438 write_misses
439 .name(name() + ".write_misses")
440 .desc("DTB write misses")
441 ;
442
443 write_acv
444 .name(name() + ".write_acv")
445 .desc("DTB write access violations")
446 ;
447
448 write_accesses
449 .name(name() + ".write_accesses")
450 .desc("DTB write accesses")
451 ;
452
453 hits
454 .name(name() + ".hits")
455 .desc("DTB hits")
456 ;
457
458 misses
459 .name(name() + ".misses")
460 .desc("DTB misses")
461 ;
462
463 acv
464 .name(name() + ".acv")
465 .desc("DTB access violations")
466 ;
467
468 accesses
469 .name(name() + ".accesses")
470 .desc("DTB accesses")
471 ;
472
473 hits = read_hits + write_hits;
474 misses = read_misses + write_misses;
475 acv = read_acv + write_acv;
476 accesses = read_accesses + write_accesses;
477}
478
479Fault
| 316{
317 //If this is a pal pc, then set PHYSICAL
318 if(FULL_SYSTEM && PcPAL(req->getPC()))
319 req->setFlags(req->getFlags() | PHYSICAL);
320
321 if (PcPAL(req->getPC())) {
322 // strip off PAL PC marker (lsb is 1)
323 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
324 hits++;
325 return NoFault;
326 }
327
328 if (req->getFlags() & PHYSICAL) {
329 req->setPaddr(req->getVaddr());
330 } else {
331 // verify that this is a good virtual address
332 if (!validVirtualAddress(req->getVaddr())) {
333 acv++;
334 return new ItbAcvFault(req->getVaddr());
335 }
336
337
338 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
339 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
340#if ALPHA_TLASER
341 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
342 VAddrSpaceEV5(req->getVaddr()) == 2)
343#else
344 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
345#endif
346 {
347 // only valid in kernel mode
348 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
349 mode_kernel) {
350 acv++;
351 return new ItbAcvFault(req->getVaddr());
352 }
353
354 req->setPaddr(req->getVaddr() & PAddrImplMask);
355
356#if !ALPHA_TLASER
357 // sign extend the physical address properly
358 if (req->getPaddr() & PAddrUncachedBit40)
359 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
360 else
361 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
362#endif
363
364 } else {
365 // not a physical address: need to look up pte
366 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
367 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
368 asn);
369
370 if (!pte) {
371 misses++;
372 return new ItbPageFault(req->getVaddr());
373 }
374
375 req->setPaddr((pte->ppn << PageShift) +
376 (VAddr(req->getVaddr()).offset()
377 & ~3));
378
379 // check permissions for this access
380 if (!(pte->xre &
381 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
382 // instruction access fault
383 acv++;
384 return new ItbAcvFault(req->getVaddr());
385 }
386
387 hits++;
388 }
389 }
390
391 // check that the physical address is ok (catch bad physical addresses)
392 if (req->getPaddr() & ~PAddrImplMask)
393 return genMachineCheckFault();
394
395 return checkCacheability(req);
396
397}
398
399///////////////////////////////////////////////////////////////////////
400//
401// Alpha DTB
402//
403 DTB::DTB(const std::string &name, int size)
404 : TLB(name, size)
405{}
406
407void
408DTB::regStats()
409{
410 read_hits
411 .name(name() + ".read_hits")
412 .desc("DTB read hits")
413 ;
414
415 read_misses
416 .name(name() + ".read_misses")
417 .desc("DTB read misses")
418 ;
419
420 read_acv
421 .name(name() + ".read_acv")
422 .desc("DTB read access violations")
423 ;
424
425 read_accesses
426 .name(name() + ".read_accesses")
427 .desc("DTB read accesses")
428 ;
429
430 write_hits
431 .name(name() + ".write_hits")
432 .desc("DTB write hits")
433 ;
434
435 write_misses
436 .name(name() + ".write_misses")
437 .desc("DTB write misses")
438 ;
439
440 write_acv
441 .name(name() + ".write_acv")
442 .desc("DTB write access violations")
443 ;
444
445 write_accesses
446 .name(name() + ".write_accesses")
447 .desc("DTB write accesses")
448 ;
449
450 hits
451 .name(name() + ".hits")
452 .desc("DTB hits")
453 ;
454
455 misses
456 .name(name() + ".misses")
457 .desc("DTB misses")
458 ;
459
460 acv
461 .name(name() + ".acv")
462 .desc("DTB access violations")
463 ;
464
465 accesses
466 .name(name() + ".accesses")
467 .desc("DTB accesses")
468 ;
469
470 hits = read_hits + write_hits;
471 misses = read_misses + write_misses;
472 acv = read_acv + write_acv;
473 accesses = read_accesses + write_accesses;
474}
475
476Fault
|
480DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
| 477DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
481{
482 Addr pc = tc->readPC();
483
484 mode_type mode =
485 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
486
487
488 /**
489 * Check for alignment faults
490 */
491 if (req->getVaddr() & (req->getSize() - 1)) {
492 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
493 req->getSize());
494 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
495 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
496 }
497
498 if (PcPAL(pc)) {
499 mode = (req->getFlags() & ALTMODE) ?
500 (mode_type)ALT_MODE_AM(
501 tc->readMiscRegNoEffect(IPR_ALT_MODE))
502 : mode_kernel;
503 }
504
505 if (req->getFlags() & PHYSICAL) {
506 req->setPaddr(req->getVaddr());
507 } else {
508 // verify that this is a good virtual address
509 if (!validVirtualAddress(req->getVaddr())) {
510 if (write) { write_acv++; } else { read_acv++; }
511 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
512 MM_STAT_BAD_VA_MASK |
513 MM_STAT_ACV_MASK;
514 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
515 }
516
517 // Check for "superpage" mapping
518#if ALPHA_TLASER
519 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
520 VAddrSpaceEV5(req->getVaddr()) == 2)
521#else
522 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
523#endif
524 {
525
526 // only valid in kernel mode
527 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
528 mode_kernel) {
529 if (write) { write_acv++; } else { read_acv++; }
530 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
531 MM_STAT_ACV_MASK);
532 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
533 }
534
535 req->setPaddr(req->getVaddr() & PAddrImplMask);
536
537#if !ALPHA_TLASER
538 // sign extend the physical address properly
539 if (req->getPaddr() & PAddrUncachedBit40)
540 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
541 else
542 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
543#endif
544
545 } else {
546 if (write)
547 write_accesses++;
548 else
549 read_accesses++;
550
551 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
552
553 // not a physical address: need to look up pte
554 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
555 asn);
556
557 if (!pte) {
558 // page fault
559 if (write) { write_misses++; } else { read_misses++; }
560 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
561 MM_STAT_DTB_MISS_MASK;
562 return (req->getFlags() & VPTE) ?
563 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
564 flags)) :
565 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
566 flags));
567 }
568
569 req->setPaddr((pte->ppn << PageShift) +
570 VAddr(req->getVaddr()).offset());
571
572 if (write) {
573 if (!(pte->xwe & MODE2MASK(mode))) {
574 // declare the instruction access fault
575 write_acv++;
576 uint64_t flags = MM_STAT_WR_MASK |
577 MM_STAT_ACV_MASK |
578 (pte->fonw ? MM_STAT_FONW_MASK : 0);
579 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
580 }
581 if (pte->fonw) {
582 write_acv++;
583 uint64_t flags = MM_STAT_WR_MASK |
584 MM_STAT_FONW_MASK;
585 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
586 }
587 } else {
588 if (!(pte->xre & MODE2MASK(mode))) {
589 read_acv++;
590 uint64_t flags = MM_STAT_ACV_MASK |
591 (pte->fonr ? MM_STAT_FONR_MASK : 0);
592 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
593 }
594 if (pte->fonr) {
595 read_acv++;
596 uint64_t flags = MM_STAT_FONR_MASK;
597 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
598 }
599 }
600 }
601
602 if (write)
603 write_hits++;
604 else
605 read_hits++;
606 }
607
608 // check that the physical address is ok (catch bad physical addresses)
609 if (req->getPaddr() & ~PAddrImplMask)
610 return genMachineCheckFault();
611
612 return checkCacheability(req);
613}
614
615PTE &
616TLB::index(bool advance)
617{
618 PTE *pte = &table[nlu];
619
620 if (advance)
621 nextnlu();
622
623 return *pte;
624}
625
626/* end namespace AlphaISA */ }
627
628AlphaISA::ITB *
629AlphaITBParams::create()
630{
631 return new AlphaISA::ITB(name, size);
632}
633
634AlphaISA::DTB *
635AlphaDTBParams::create()
636{
637 return new AlphaISA::DTB(name, size);
638}
| 478{
479 Addr pc = tc->readPC();
480
481 mode_type mode =
482 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
483
484
485 /**
486 * Check for alignment faults
487 */
488 if (req->getVaddr() & (req->getSize() - 1)) {
489 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
490 req->getSize());
491 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
492 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
493 }
494
495 if (PcPAL(pc)) {
496 mode = (req->getFlags() & ALTMODE) ?
497 (mode_type)ALT_MODE_AM(
498 tc->readMiscRegNoEffect(IPR_ALT_MODE))
499 : mode_kernel;
500 }
501
502 if (req->getFlags() & PHYSICAL) {
503 req->setPaddr(req->getVaddr());
504 } else {
505 // verify that this is a good virtual address
506 if (!validVirtualAddress(req->getVaddr())) {
507 if (write) { write_acv++; } else { read_acv++; }
508 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
509 MM_STAT_BAD_VA_MASK |
510 MM_STAT_ACV_MASK;
511 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
512 }
513
514 // Check for "superpage" mapping
515#if ALPHA_TLASER
516 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
517 VAddrSpaceEV5(req->getVaddr()) == 2)
518#else
519 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
520#endif
521 {
522
523 // only valid in kernel mode
524 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
525 mode_kernel) {
526 if (write) { write_acv++; } else { read_acv++; }
527 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
528 MM_STAT_ACV_MASK);
529 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
530 }
531
532 req->setPaddr(req->getVaddr() & PAddrImplMask);
533
534#if !ALPHA_TLASER
535 // sign extend the physical address properly
536 if (req->getPaddr() & PAddrUncachedBit40)
537 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
538 else
539 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
540#endif
541
542 } else {
543 if (write)
544 write_accesses++;
545 else
546 read_accesses++;
547
548 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
549
550 // not a physical address: need to look up pte
551 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
552 asn);
553
554 if (!pte) {
555 // page fault
556 if (write) { write_misses++; } else { read_misses++; }
557 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
558 MM_STAT_DTB_MISS_MASK;
559 return (req->getFlags() & VPTE) ?
560 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
561 flags)) :
562 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
563 flags));
564 }
565
566 req->setPaddr((pte->ppn << PageShift) +
567 VAddr(req->getVaddr()).offset());
568
569 if (write) {
570 if (!(pte->xwe & MODE2MASK(mode))) {
571 // declare the instruction access fault
572 write_acv++;
573 uint64_t flags = MM_STAT_WR_MASK |
574 MM_STAT_ACV_MASK |
575 (pte->fonw ? MM_STAT_FONW_MASK : 0);
576 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
577 }
578 if (pte->fonw) {
579 write_acv++;
580 uint64_t flags = MM_STAT_WR_MASK |
581 MM_STAT_FONW_MASK;
582 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
583 }
584 } else {
585 if (!(pte->xre & MODE2MASK(mode))) {
586 read_acv++;
587 uint64_t flags = MM_STAT_ACV_MASK |
588 (pte->fonr ? MM_STAT_FONR_MASK : 0);
589 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
590 }
591 if (pte->fonr) {
592 read_acv++;
593 uint64_t flags = MM_STAT_FONR_MASK;
594 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
595 }
596 }
597 }
598
599 if (write)
600 write_hits++;
601 else
602 read_hits++;
603 }
604
605 // check that the physical address is ok (catch bad physical addresses)
606 if (req->getPaddr() & ~PAddrImplMask)
607 return genMachineCheckFault();
608
609 return checkCacheability(req);
610}
611
612PTE &
613TLB::index(bool advance)
614{
615 PTE *pte = &table[nlu];
616
617 if (advance)
618 nextnlu();
619
620 return *pte;
621}
622
623/* end namespace AlphaISA */ }
624
625AlphaISA::ITB *
626AlphaITBParams::create()
627{
628 return new AlphaISA::ITB(name, size);
629}
630
631AlphaISA::DTB *
632AlphaDTBParams::create()
633{
634 return new AlphaISA::DTB(name, size);
635}
|