1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 */
28
29#include <string>
30#include <vector>
31
32#include "arch/alpha/tlb.hh"
33#include "base/inifile.hh"
34#include "base/str.hh"
35#include "base/trace.hh"
36#include "config/alpha_tlaser.hh"
37#include "cpu/exec_context.hh"
38#include "sim/builder.hh"
39
40using namespace std;
41using namespace EV5;
42
43///////////////////////////////////////////////////////////////////////
44//
45// Alpha TLB
46//
47#ifdef DEBUG
48bool uncacheBit39 = false;
49bool uncacheBit40 = false;
50#endif
51
52#define MODE2MASK(X) (1 << (X))
53
54AlphaTLB::AlphaTLB(const string &name, int s)
55 : SimObject(name), size(s), nlu(0)
56{
57 table = new AlphaISA::PTE[size];
58 memset(table, 0, sizeof(AlphaISA::PTE[size]));
59}
60
61AlphaTLB::~AlphaTLB()
62{
63 if (table)
64 delete [] table;
65}
66
67// look up an entry in the TLB
68AlphaISA::PTE *
69AlphaTLB::lookup(Addr vpn, uint8_t asn) const
70{
71 // assume not found...
72 AlphaISA::PTE *retval = NULL;
73
74 PageTable::const_iterator i = lookupTable.find(vpn);
75 if (i != lookupTable.end()) {
76 while (i->first == vpn) {
77 int index = i->second;
78 AlphaISA::PTE *pte = &table[index];
79 assert(pte->valid);
80 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
81 retval = pte;
82 break;
83 }
84
85 ++i;
86 }
87 }
88
89 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
90 retval ? "hit" : "miss", retval ? retval->ppn : 0);
91 return retval;
92}
93
94
95Fault
96AlphaTLB::checkCacheability(RequestPtr &req)
97{
98 // in Alpha, cacheability is controlled by upper-level bits of the
99 // physical address
100
101 /*
102 * We support having the uncacheable bit in either bit 39 or bit 40.
103 * The Turbolaser platform (and EV5) support having the bit in 39, but
104 * Tsunami (which Linux assumes uses an EV6) generates accesses with
105 * the bit in 40. So we must check for both, but we have debug flags
106 * to catch a weird case where both are used, which shouldn't happen.
107 */
108
109
110#if ALPHA_TLASER
111 if (req->getPaddr() & PAddrUncachedBit39) {
112#else
113 if (req->getPaddr() & PAddrUncachedBit43) {
114#endif
115 // IPR memory space not implemented
116 if (PAddrIprSpace(req->getPaddr())) {
117 return new UnimpFault("IPR memory space not implemented!");
118 } else {
119 // mark request as uncacheable
120 req->setFlags(req->getFlags() | UNCACHEABLE);
121
122#if !ALPHA_TLASER
123 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
124 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
125#endif
126 }
127 }
128 return NoFault;
129}
130
131
132// insert a new TLB entry
133void
134AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
135{
136 AlphaISA::VAddr vaddr = addr;
137 if (table[nlu].valid) {
138 Addr oldvpn = table[nlu].tag;
139 PageTable::iterator i = lookupTable.find(oldvpn);
140
141 if (i == lookupTable.end())
142 panic("TLB entry not found in lookupTable");
143
144 int index;
145 while ((index = i->second) != nlu) {
146 if (table[index].tag != oldvpn)
147 panic("TLB entry not found in lookupTable");
148
149 ++i;
150 }
151
152 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
153
154 lookupTable.erase(i);
155 }
156
157 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
158
159 table[nlu] = pte;
160 table[nlu].tag = vaddr.vpn();
161 table[nlu].valid = true;
162
163 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
164 nextnlu();
165}
166
167void
168AlphaTLB::flushAll()
169{
170 DPRINTF(TLB, "flushAll\n");
171 memset(table, 0, sizeof(AlphaISA::PTE[size]));
172 lookupTable.clear();
173 nlu = 0;
174}
175
176void
177AlphaTLB::flushProcesses()
178{
179 PageTable::iterator i = lookupTable.begin();
180 PageTable::iterator end = lookupTable.end();
181 while (i != end) {
182 int index = i->second;
183 AlphaISA::PTE *pte = &table[index];
184 assert(pte->valid);
185
186 // we can't increment i after we erase it, so save a copy and
187 // increment it to get the next entry now
188 PageTable::iterator cur = i;
189 ++i;
190
191 if (!pte->asma) {
192 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
193 pte->valid = false;
194 lookupTable.erase(cur);
195 }
196 }
197}
198
199void
200AlphaTLB::flushAddr(Addr addr, uint8_t asn)
201{
202 AlphaISA::VAddr vaddr = addr;
203
204 PageTable::iterator i = lookupTable.find(vaddr.vpn());
205 if (i == lookupTable.end())
206 return;
207
208 while (i->first == vaddr.vpn()) {
209 int index = i->second;
210 AlphaISA::PTE *pte = &table[index];
211 assert(pte->valid);
212
213 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
214 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
215 pte->ppn);
216
217 // invalidate this entry
218 pte->valid = false;
219
220 lookupTable.erase(i);
221 }
222
223 ++i;
224 }
225}
226
227
228void
229AlphaTLB::serialize(ostream &os)
230{
231 SERIALIZE_SCALAR(size);
232 SERIALIZE_SCALAR(nlu);
233
234 for (int i = 0; i < size; i++) {
235 nameOut(os, csprintf("%s.PTE%d", name(), i));
236 table[i].serialize(os);
237 }
238}
239
240void
241AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
242{
243 UNSERIALIZE_SCALAR(size);
244 UNSERIALIZE_SCALAR(nlu);
245
246 for (int i = 0; i < size; i++) {
247 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
248 if (table[i].valid) {
249 lookupTable.insert(make_pair(table[i].tag, i));
250 }
251 }
252}
253
254
255///////////////////////////////////////////////////////////////////////
256//
257// Alpha ITB
258//
259AlphaITB::AlphaITB(const std::string &name, int size)
260 : AlphaTLB(name, size)
261{}
262
263
264void
265AlphaITB::regStats()
266{
267 hits
268 .name(name() + ".hits")
269 .desc("ITB hits");
270 misses
271 .name(name() + ".misses")
272 .desc("ITB misses");
273 acv
274 .name(name() + ".acv")
275 .desc("ITB acv");
276 accesses
277 .name(name() + ".accesses")
278 .desc("ITB accesses");
279
280 accesses = hits + misses;
281}
282
283
284Fault
285AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
286{
287 if (AlphaISA::PcPAL(req->getVaddr())) {
288 // strip off PAL PC marker (lsb is 1)
289 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
290 hits++;
291 return NoFault;
292 }
293
294 if (req->getFlags() & PHYSICAL) {
295 req->setPaddr(req->getVaddr());
296 } else {
297 // verify that this is a good virtual address
298 if (!validVirtualAddress(req->getVaddr())) {
299 acv++;
300 return new ItbAcvFault(req->getVaddr());
301 }
302
303
304 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
305 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
306#if ALPHA_TLASER
307 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
308 VAddrSpaceEV5(req->getVaddr()) == 2) {
309#else
310 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
311#endif
312 // only valid in kernel mode
313 if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
314 AlphaISA::mode_kernel) {
315 acv++;
316 return new ItbAcvFault(req->getVaddr());
317 }
318
319 req->setPaddr(req->getVaddr() & PAddrImplMask);
320
321#if !ALPHA_TLASER
322 // sign extend the physical address properly
323 if (req->getPaddr() & PAddrUncachedBit40)
324 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
325 else
326 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
327#endif
328
329 } else {
330 // not a physical address: need to look up pte
331 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
332 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
333 asn);
334
335 if (!pte) {
336 misses++;
337 return new ItbPageFault(req->getVaddr());
338 }
339
340 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
341 (AlphaISA::VAddr(req->getVaddr()).offset()
342 & ~3));
343
344 // check permissions for this access
345 if (!(pte->xre &
346 (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
347 // instruction access fault
348 acv++;
349 return new ItbAcvFault(req->getVaddr());
350 }
351
352 hits++;
353 }
354 }
355
356 // check that the physical address is ok (catch bad physical addresses)
357 if (req->getPaddr() & ~PAddrImplMask)
358 return genMachineCheckFault();
359
360 return checkCacheability(req);
361
362}
363
364///////////////////////////////////////////////////////////////////////
365//
366// Alpha DTB
367//
368AlphaDTB::AlphaDTB(const std::string &name, int size)
369 : AlphaTLB(name, size)
370{}
371
372void
373AlphaDTB::regStats()
374{
375 read_hits
376 .name(name() + ".read_hits")
377 .desc("DTB read hits")
378 ;
379
380 read_misses
381 .name(name() + ".read_misses")
382 .desc("DTB read misses")
383 ;
384
385 read_acv
386 .name(name() + ".read_acv")
387 .desc("DTB read access violations")
388 ;
389
390 read_accesses
391 .name(name() + ".read_accesses")
392 .desc("DTB read accesses")
393 ;
394
395 write_hits
396 .name(name() + ".write_hits")
397 .desc("DTB write hits")
398 ;
399
400 write_misses
401 .name(name() + ".write_misses")
402 .desc("DTB write misses")
403 ;
404
405 write_acv
406 .name(name() + ".write_acv")
407 .desc("DTB write access violations")
408 ;
409
410 write_accesses
411 .name(name() + ".write_accesses")
412 .desc("DTB write accesses")
413 ;
414
415 hits
416 .name(name() + ".hits")
417 .desc("DTB hits")
418 ;
419
420 misses
421 .name(name() + ".misses")
422 .desc("DTB misses")
423 ;
424
425 acv
426 .name(name() + ".acv")
427 .desc("DTB access violations")
428 ;
429
430 accesses
431 .name(name() + ".accesses")
432 .desc("DTB accesses")
433 ;
434
435 hits = read_hits + write_hits;
436 misses = read_misses + write_misses;
437 acv = read_acv + write_acv;
438 accesses = read_accesses + write_accesses;
439}
440
441Fault
442AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
443{
444 Addr pc = xc->readPC();
445
446 AlphaISA::mode_type mode =
447 (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
448
449
450 /**
451 * Check for alignment faults
452 */
453 if (req->getVaddr() & (req->getSize() - 1)) {
454 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
455 req->getSize());
456 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
457 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
458 }
459
460 if (pc & 0x1) {
461 mode = (req->getFlags() & ALTMODE) ?
462 (AlphaISA::mode_type)ALT_MODE_AM(
463 xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
464 : AlphaISA::mode_kernel;
465 }
466
467 if (req->getFlags() & PHYSICAL) {
468 req->setPaddr(req->getVaddr());
469 } else {
470 // verify that this is a good virtual address
471 if (!validVirtualAddress(req->getVaddr())) {
472 if (write) { write_acv++; } else { read_acv++; }
473 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
474 MM_STAT_BAD_VA_MASK |
475 MM_STAT_ACV_MASK;
476 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
477 }
478
479 // Check for "superpage" mapping
480#if ALPHA_TLASER
481 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
482 VAddrSpaceEV5(req->getVaddr()) == 2) {
483#else
484 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
485#endif
486
487 // only valid in kernel mode
488 if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
489 AlphaISA::mode_kernel) {
490 if (write) { write_acv++; } else { read_acv++; }
491 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
492 MM_STAT_ACV_MASK);
493 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
494 }
495
496 req->setPaddr(req->getVaddr() & PAddrImplMask);
497
498#if !ALPHA_TLASER
499 // sign extend the physical address properly
500 if (req->getPaddr() & PAddrUncachedBit40)
501 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
502 else
503 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
504#endif
505
506 } else {
507 if (write)
508 write_accesses++;
509 else
510 read_accesses++;
511
512 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
513
514 // not a physical address: need to look up pte
515 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
516 asn);
517
518 if (!pte) {
519 // page fault
520 if (write) { write_misses++; } else { read_misses++; }
521 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
522 MM_STAT_DTB_MISS_MASK;
523 return (req->getFlags() & VPTE) ?
524 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
525 flags)) :
526 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
527 flags));
528 }
529
530 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
531 AlphaISA::VAddr(req->getVaddr()).offset());
532
533 if (write) {
534 if (!(pte->xwe & MODE2MASK(mode))) {
535 // declare the instruction access fault
536 write_acv++;
537 uint64_t flags = MM_STAT_WR_MASK |
538 MM_STAT_ACV_MASK |
539 (pte->fonw ? MM_STAT_FONW_MASK : 0);
540 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
541 }
542 if (pte->fonw) {
543 write_acv++;
544 uint64_t flags = MM_STAT_WR_MASK |
545 MM_STAT_FONW_MASK;
546 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
547 }
548 } else {
549 if (!(pte->xre & MODE2MASK(mode))) {
550 read_acv++;
551 uint64_t flags = MM_STAT_ACV_MASK |
552 (pte->fonr ? MM_STAT_FONR_MASK : 0);
553 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
554 }
555 if (pte->fonr) {
556 read_acv++;
557 uint64_t flags = MM_STAT_FONR_MASK;
558 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
559 }
560 }
561 }
562
563 if (write)
564 write_hits++;
565 else
566 read_hits++;
567 }
568
569 // check that the physical address is ok (catch bad physical addresses)
570 if (req->getPaddr() & ~PAddrImplMask)
571 return genMachineCheckFault();
572
573 return checkCacheability(req);
574}
575
576AlphaISA::PTE &
577AlphaTLB::index(bool advance)
578{
579 AlphaISA::PTE *pte = &table[nlu];
580
581 if (advance)
582 nextnlu();
583
584 return *pte;
585}
586
587DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
588
589BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
590
591 Param<int> size;
592
593END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
594
595BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
596
597 INIT_PARAM_DFLT(size, "TLB size", 48)
598
599END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
600
601
602CREATE_SIM_OBJECT(AlphaITB)
603{
604 return new AlphaITB(getInstanceName(), size);
605}
606
607REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
608
609BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
610
611 Param<int> size;
612
613END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
614
615BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
616
617 INIT_PARAM_DFLT(size, "TLB size", 64)
618
619END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
620
621
622CREATE_SIM_OBJECT(AlphaDTB)
623{
624 return new AlphaDTB(getInstanceName(), size);
625}
626
627REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
628
| 31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/tlb.hh"
37#include "base/inifile.hh"
38#include "base/str.hh"
39#include "base/trace.hh"
40#include "config/alpha_tlaser.hh"
41#include "cpu/exec_context.hh"
42#include "sim/builder.hh"
43
44using namespace std;
45using namespace EV5;
46
47///////////////////////////////////////////////////////////////////////
48//
49// Alpha TLB
50//
51#ifdef DEBUG
52bool uncacheBit39 = false;
53bool uncacheBit40 = false;
54#endif
55
56#define MODE2MASK(X) (1 << (X))
57
58AlphaTLB::AlphaTLB(const string &name, int s)
59 : SimObject(name), size(s), nlu(0)
60{
61 table = new AlphaISA::PTE[size];
62 memset(table, 0, sizeof(AlphaISA::PTE[size]));
63}
64
65AlphaTLB::~AlphaTLB()
66{
67 if (table)
68 delete [] table;
69}
70
71// look up an entry in the TLB
72AlphaISA::PTE *
73AlphaTLB::lookup(Addr vpn, uint8_t asn) const
74{
75 // assume not found...
76 AlphaISA::PTE *retval = NULL;
77
78 PageTable::const_iterator i = lookupTable.find(vpn);
79 if (i != lookupTable.end()) {
80 while (i->first == vpn) {
81 int index = i->second;
82 AlphaISA::PTE *pte = &table[index];
83 assert(pte->valid);
84 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
85 retval = pte;
86 break;
87 }
88
89 ++i;
90 }
91 }
92
93 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
94 retval ? "hit" : "miss", retval ? retval->ppn : 0);
95 return retval;
96}
97
98
99Fault
100AlphaTLB::checkCacheability(RequestPtr &req)
101{
102 // in Alpha, cacheability is controlled by upper-level bits of the
103 // physical address
104
105 /*
106 * We support having the uncacheable bit in either bit 39 or bit 40.
107 * The Turbolaser platform (and EV5) support having the bit in 39, but
108 * Tsunami (which Linux assumes uses an EV6) generates accesses with
109 * the bit in 40. So we must check for both, but we have debug flags
110 * to catch a weird case where both are used, which shouldn't happen.
111 */
112
113
114#if ALPHA_TLASER
115 if (req->getPaddr() & PAddrUncachedBit39) {
116#else
117 if (req->getPaddr() & PAddrUncachedBit43) {
118#endif
119 // IPR memory space not implemented
120 if (PAddrIprSpace(req->getPaddr())) {
121 return new UnimpFault("IPR memory space not implemented!");
122 } else {
123 // mark request as uncacheable
124 req->setFlags(req->getFlags() | UNCACHEABLE);
125
126#if !ALPHA_TLASER
127 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
128 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
129#endif
130 }
131 }
132 return NoFault;
133}
134
135
136// insert a new TLB entry
137void
138AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
139{
140 AlphaISA::VAddr vaddr = addr;
141 if (table[nlu].valid) {
142 Addr oldvpn = table[nlu].tag;
143 PageTable::iterator i = lookupTable.find(oldvpn);
144
145 if (i == lookupTable.end())
146 panic("TLB entry not found in lookupTable");
147
148 int index;
149 while ((index = i->second) != nlu) {
150 if (table[index].tag != oldvpn)
151 panic("TLB entry not found in lookupTable");
152
153 ++i;
154 }
155
156 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
157
158 lookupTable.erase(i);
159 }
160
161 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
162
163 table[nlu] = pte;
164 table[nlu].tag = vaddr.vpn();
165 table[nlu].valid = true;
166
167 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
168 nextnlu();
169}
170
171void
172AlphaTLB::flushAll()
173{
174 DPRINTF(TLB, "flushAll\n");
175 memset(table, 0, sizeof(AlphaISA::PTE[size]));
176 lookupTable.clear();
177 nlu = 0;
178}
179
180void
181AlphaTLB::flushProcesses()
182{
183 PageTable::iterator i = lookupTable.begin();
184 PageTable::iterator end = lookupTable.end();
185 while (i != end) {
186 int index = i->second;
187 AlphaISA::PTE *pte = &table[index];
188 assert(pte->valid);
189
190 // we can't increment i after we erase it, so save a copy and
191 // increment it to get the next entry now
192 PageTable::iterator cur = i;
193 ++i;
194
195 if (!pte->asma) {
196 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
197 pte->valid = false;
198 lookupTable.erase(cur);
199 }
200 }
201}
202
203void
204AlphaTLB::flushAddr(Addr addr, uint8_t asn)
205{
206 AlphaISA::VAddr vaddr = addr;
207
208 PageTable::iterator i = lookupTable.find(vaddr.vpn());
209 if (i == lookupTable.end())
210 return;
211
212 while (i->first == vaddr.vpn()) {
213 int index = i->second;
214 AlphaISA::PTE *pte = &table[index];
215 assert(pte->valid);
216
217 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
218 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
219 pte->ppn);
220
221 // invalidate this entry
222 pte->valid = false;
223
224 lookupTable.erase(i);
225 }
226
227 ++i;
228 }
229}
230
231
232void
233AlphaTLB::serialize(ostream &os)
234{
235 SERIALIZE_SCALAR(size);
236 SERIALIZE_SCALAR(nlu);
237
238 for (int i = 0; i < size; i++) {
239 nameOut(os, csprintf("%s.PTE%d", name(), i));
240 table[i].serialize(os);
241 }
242}
243
244void
245AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
246{
247 UNSERIALIZE_SCALAR(size);
248 UNSERIALIZE_SCALAR(nlu);
249
250 for (int i = 0; i < size; i++) {
251 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
252 if (table[i].valid) {
253 lookupTable.insert(make_pair(table[i].tag, i));
254 }
255 }
256}
257
258
259///////////////////////////////////////////////////////////////////////
260//
261// Alpha ITB
262//
263AlphaITB::AlphaITB(const std::string &name, int size)
264 : AlphaTLB(name, size)
265{}
266
267
268void
269AlphaITB::regStats()
270{
271 hits
272 .name(name() + ".hits")
273 .desc("ITB hits");
274 misses
275 .name(name() + ".misses")
276 .desc("ITB misses");
277 acv
278 .name(name() + ".acv")
279 .desc("ITB acv");
280 accesses
281 .name(name() + ".accesses")
282 .desc("ITB accesses");
283
284 accesses = hits + misses;
285}
286
287
288Fault
289AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
290{
291 if (AlphaISA::PcPAL(req->getVaddr())) {
292 // strip off PAL PC marker (lsb is 1)
293 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
294 hits++;
295 return NoFault;
296 }
297
298 if (req->getFlags() & PHYSICAL) {
299 req->setPaddr(req->getVaddr());
300 } else {
301 // verify that this is a good virtual address
302 if (!validVirtualAddress(req->getVaddr())) {
303 acv++;
304 return new ItbAcvFault(req->getVaddr());
305 }
306
307
308 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
309 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
310#if ALPHA_TLASER
311 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
312 VAddrSpaceEV5(req->getVaddr()) == 2) {
313#else
314 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
315#endif
316 // only valid in kernel mode
317 if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
318 AlphaISA::mode_kernel) {
319 acv++;
320 return new ItbAcvFault(req->getVaddr());
321 }
322
323 req->setPaddr(req->getVaddr() & PAddrImplMask);
324
325#if !ALPHA_TLASER
326 // sign extend the physical address properly
327 if (req->getPaddr() & PAddrUncachedBit40)
328 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
329 else
330 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
331#endif
332
333 } else {
334 // not a physical address: need to look up pte
335 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
336 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
337 asn);
338
339 if (!pte) {
340 misses++;
341 return new ItbPageFault(req->getVaddr());
342 }
343
344 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
345 (AlphaISA::VAddr(req->getVaddr()).offset()
346 & ~3));
347
348 // check permissions for this access
349 if (!(pte->xre &
350 (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
351 // instruction access fault
352 acv++;
353 return new ItbAcvFault(req->getVaddr());
354 }
355
356 hits++;
357 }
358 }
359
360 // check that the physical address is ok (catch bad physical addresses)
361 if (req->getPaddr() & ~PAddrImplMask)
362 return genMachineCheckFault();
363
364 return checkCacheability(req);
365
366}
367
368///////////////////////////////////////////////////////////////////////
369//
370// Alpha DTB
371//
372AlphaDTB::AlphaDTB(const std::string &name, int size)
373 : AlphaTLB(name, size)
374{}
375
376void
377AlphaDTB::regStats()
378{
379 read_hits
380 .name(name() + ".read_hits")
381 .desc("DTB read hits")
382 ;
383
384 read_misses
385 .name(name() + ".read_misses")
386 .desc("DTB read misses")
387 ;
388
389 read_acv
390 .name(name() + ".read_acv")
391 .desc("DTB read access violations")
392 ;
393
394 read_accesses
395 .name(name() + ".read_accesses")
396 .desc("DTB read accesses")
397 ;
398
399 write_hits
400 .name(name() + ".write_hits")
401 .desc("DTB write hits")
402 ;
403
404 write_misses
405 .name(name() + ".write_misses")
406 .desc("DTB write misses")
407 ;
408
409 write_acv
410 .name(name() + ".write_acv")
411 .desc("DTB write access violations")
412 ;
413
414 write_accesses
415 .name(name() + ".write_accesses")
416 .desc("DTB write accesses")
417 ;
418
419 hits
420 .name(name() + ".hits")
421 .desc("DTB hits")
422 ;
423
424 misses
425 .name(name() + ".misses")
426 .desc("DTB misses")
427 ;
428
429 acv
430 .name(name() + ".acv")
431 .desc("DTB access violations")
432 ;
433
434 accesses
435 .name(name() + ".accesses")
436 .desc("DTB accesses")
437 ;
438
439 hits = read_hits + write_hits;
440 misses = read_misses + write_misses;
441 acv = read_acv + write_acv;
442 accesses = read_accesses + write_accesses;
443}
444
445Fault
446AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
447{
448 Addr pc = xc->readPC();
449
450 AlphaISA::mode_type mode =
451 (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
452
453
454 /**
455 * Check for alignment faults
456 */
457 if (req->getVaddr() & (req->getSize() - 1)) {
458 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
459 req->getSize());
460 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
461 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
462 }
463
464 if (pc & 0x1) {
465 mode = (req->getFlags() & ALTMODE) ?
466 (AlphaISA::mode_type)ALT_MODE_AM(
467 xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
468 : AlphaISA::mode_kernel;
469 }
470
471 if (req->getFlags() & PHYSICAL) {
472 req->setPaddr(req->getVaddr());
473 } else {
474 // verify that this is a good virtual address
475 if (!validVirtualAddress(req->getVaddr())) {
476 if (write) { write_acv++; } else { read_acv++; }
477 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
478 MM_STAT_BAD_VA_MASK |
479 MM_STAT_ACV_MASK;
480 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
481 }
482
483 // Check for "superpage" mapping
484#if ALPHA_TLASER
485 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
486 VAddrSpaceEV5(req->getVaddr()) == 2) {
487#else
488 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
489#endif
490
491 // only valid in kernel mode
492 if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
493 AlphaISA::mode_kernel) {
494 if (write) { write_acv++; } else { read_acv++; }
495 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
496 MM_STAT_ACV_MASK);
497 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
498 }
499
500 req->setPaddr(req->getVaddr() & PAddrImplMask);
501
502#if !ALPHA_TLASER
503 // sign extend the physical address properly
504 if (req->getPaddr() & PAddrUncachedBit40)
505 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
506 else
507 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
508#endif
509
510 } else {
511 if (write)
512 write_accesses++;
513 else
514 read_accesses++;
515
516 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
517
518 // not a physical address: need to look up pte
519 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
520 asn);
521
522 if (!pte) {
523 // page fault
524 if (write) { write_misses++; } else { read_misses++; }
525 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
526 MM_STAT_DTB_MISS_MASK;
527 return (req->getFlags() & VPTE) ?
528 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
529 flags)) :
530 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
531 flags));
532 }
533
534 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
535 AlphaISA::VAddr(req->getVaddr()).offset());
536
537 if (write) {
538 if (!(pte->xwe & MODE2MASK(mode))) {
539 // declare the instruction access fault
540 write_acv++;
541 uint64_t flags = MM_STAT_WR_MASK |
542 MM_STAT_ACV_MASK |
543 (pte->fonw ? MM_STAT_FONW_MASK : 0);
544 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
545 }
546 if (pte->fonw) {
547 write_acv++;
548 uint64_t flags = MM_STAT_WR_MASK |
549 MM_STAT_FONW_MASK;
550 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
551 }
552 } else {
553 if (!(pte->xre & MODE2MASK(mode))) {
554 read_acv++;
555 uint64_t flags = MM_STAT_ACV_MASK |
556 (pte->fonr ? MM_STAT_FONR_MASK : 0);
557 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
558 }
559 if (pte->fonr) {
560 read_acv++;
561 uint64_t flags = MM_STAT_FONR_MASK;
562 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
563 }
564 }
565 }
566
567 if (write)
568 write_hits++;
569 else
570 read_hits++;
571 }
572
573 // check that the physical address is ok (catch bad physical addresses)
574 if (req->getPaddr() & ~PAddrImplMask)
575 return genMachineCheckFault();
576
577 return checkCacheability(req);
578}
579
580AlphaISA::PTE &
581AlphaTLB::index(bool advance)
582{
583 AlphaISA::PTE *pte = &table[nlu];
584
585 if (advance)
586 nextnlu();
587
588 return *pte;
589}
590
591DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
592
593BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
594
595 Param<int> size;
596
597END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
598
599BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
600
601 INIT_PARAM_DFLT(size, "TLB size", 48)
602
603END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
604
605
606CREATE_SIM_OBJECT(AlphaITB)
607{
608 return new AlphaITB(getInstanceName(), size);
609}
610
611REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
612
613BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
614
615 Param<int> size;
616
617END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
618
619BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
620
621 INIT_PARAM_DFLT(size, "TLB size", 64)
622
623END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
624
625
626CREATE_SIM_OBJECT(AlphaDTB)
627{
628 return new AlphaDTB(getInstanceName(), size);
629}
630
631REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
632
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