tlb.cc (6023:47b4fcb10c11) | tlb.cc (6025:044903442dcb) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include <vector> 35 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include <vector> 35 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" |
42#include "config/alpha_tlaser.hh" | |
43#include "cpu/thread_context.hh" 44 45using namespace std; 46 47namespace AlphaISA { 48 49/////////////////////////////////////////////////////////////////////// 50// --- 159 unchanged lines hidden (view full) --- 210 * 40. The Turbolaser platform (and EV5) support having the bit 211 * in 39, but Tsunami (which Linux assumes uses an EV6) generates 212 * accesses with the bit in 40. So we must check for both, but we 213 * have debug flags to catch a weird case where both are used, 214 * which shouldn't happen. 215 */ 216 217 | 42#include "cpu/thread_context.hh" 43 44using namespace std; 45 46namespace AlphaISA { 47 48/////////////////////////////////////////////////////////////////////// 49// --- 159 unchanged lines hidden (view full) --- 209 * 40. The Turbolaser platform (and EV5) support having the bit 210 * in 39, but Tsunami (which Linux assumes uses an EV6) generates 211 * accesses with the bit in 40. So we must check for both, but we 212 * have debug flags to catch a weird case where both are used, 213 * which shouldn't happen. 214 */ 215 216 |
218#if ALPHA_TLASER 219 if (req->getPaddr() & PAddrUncachedBit39) 220#else 221 if (req->getPaddr() & PAddrUncachedBit43) 222#endif 223 { | 217 if (req->getPaddr() & PAddrUncachedBit43) { |
224 // IPR memory space not implemented 225 if (PAddrIprSpace(req->getPaddr())) { 226 return new UnimpFault("IPR memory space not implemented!"); 227 } else { 228 // mark request as uncacheable 229 req->setFlags(Request::UNCACHEABLE); 230 | 218 // IPR memory space not implemented 219 if (PAddrIprSpace(req->getPaddr())) { 220 return new UnimpFault("IPR memory space not implemented!"); 221 } else { 222 // mark request as uncacheable 223 req->setFlags(Request::UNCACHEABLE); 224 |
231#if !ALPHA_TLASER | |
232 // Clear bits 42:35 of the physical address (10-2 in 233 // Tsunami manual) 234 req->setPaddr(req->getPaddr() & PAddrUncachedMask); | 225 // Clear bits 42:35 of the physical address (10-2 in 226 // Tsunami manual) 227 req->setPaddr(req->getPaddr() & PAddrUncachedMask); |
235#endif | |
236 } 237 // We shouldn't be able to read from an uncachable address in Alpha as 238 // we don't have a ROM and we don't want to try to fetch from a device 239 // register as we destroy any data that is clear-on-read. 240 if (req->isUncacheable() && itb) 241 return new UnimpFault("CPU trying to fetch from uncached I/O"); 242 243 } --- 149 unchanged lines hidden (view full) --- 393 if (!validVirtualAddress(req->getVaddr())) { 394 fetch_acv++; 395 return new ItbAcvFault(req->getVaddr()); 396 } 397 398 399 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 400 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 | 228 } 229 // We shouldn't be able to read from an uncachable address in Alpha as 230 // we don't have a ROM and we don't want to try to fetch from a device 231 // register as we destroy any data that is clear-on-read. 232 if (req->isUncacheable() && itb) 233 return new UnimpFault("CPU trying to fetch from uncached I/O"); 234 235 } --- 149 unchanged lines hidden (view full) --- 385 if (!validVirtualAddress(req->getVaddr())) { 386 fetch_acv++; 387 return new ItbAcvFault(req->getVaddr()); 388 } 389 390 391 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 392 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 |
401#if ALPHA_TLASER 402 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 403 VAddrSpaceEV5(req->getVaddr()) == 2) 404#else 405 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 406#endif 407 { | 393 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
408 // only valid in kernel mode 409 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 410 mode_kernel) { 411 fetch_acv++; 412 return new ItbAcvFault(req->getVaddr()); 413 } 414 415 req->setPaddr(req->getVaddr() & PAddrImplMask); 416 | 394 // only valid in kernel mode 395 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 396 mode_kernel) { 397 fetch_acv++; 398 return new ItbAcvFault(req->getVaddr()); 399 } 400 401 req->setPaddr(req->getVaddr() & PAddrImplMask); 402 |
417#if !ALPHA_TLASER | |
418 // sign extend the physical address properly 419 if (req->getPaddr() & PAddrUncachedBit40) 420 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 421 else 422 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); | 403 // sign extend the physical address properly 404 if (req->getPaddr() & PAddrUncachedBit40) 405 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 406 else 407 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
423#endif 424 | |
425 } else { 426 // not a physical address: need to look up pte 427 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 428 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 429 asn); 430 431 if (!entry) { 432 fetch_misses++; --- 57 unchanged lines hidden (view full) --- 490 if (write) { write_acv++; } else { read_acv++; } 491 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 492 MM_STAT_BAD_VA_MASK | 493 MM_STAT_ACV_MASK; 494 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 495 } 496 497 // Check for "superpage" mapping | 408 } else { 409 // not a physical address: need to look up pte 410 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 411 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 412 asn); 413 414 if (!entry) { 415 fetch_misses++; --- 57 unchanged lines hidden (view full) --- 473 if (write) { write_acv++; } else { read_acv++; } 474 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 475 MM_STAT_BAD_VA_MASK | 476 MM_STAT_ACV_MASK; 477 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 478 } 479 480 // Check for "superpage" mapping |
498#if ALPHA_TLASER 499 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 500 VAddrSpaceEV5(req->getVaddr()) == 2) 501#else 502 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 503#endif 504 { | 481 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
505 // only valid in kernel mode 506 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 507 mode_kernel) { 508 if (write) { write_acv++; } else { read_acv++; } 509 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 510 MM_STAT_ACV_MASK); 511 512 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 513 flags); 514 } 515 516 req->setPaddr(req->getVaddr() & PAddrImplMask); 517 | 482 // only valid in kernel mode 483 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 484 mode_kernel) { 485 if (write) { write_acv++; } else { read_acv++; } 486 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 487 MM_STAT_ACV_MASK); 488 489 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 490 flags); 491 } 492 493 req->setPaddr(req->getVaddr() & PAddrImplMask); 494 |
518#if !ALPHA_TLASER | |
519 // sign extend the physical address properly 520 if (req->getPaddr() & PAddrUncachedBit40) 521 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 522 else 523 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); | 495 // sign extend the physical address properly 496 if (req->getPaddr() & PAddrUncachedBit40) 497 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 498 else 499 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
524#endif 525 | |
526 } else { 527 if (write) 528 write_accesses++; 529 else 530 read_accesses++; 531 532 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 533 --- 99 unchanged lines hidden --- | 500 } else { 501 if (write) 502 write_accesses++; 503 else 504 read_accesses++; 505 506 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 507 --- 99 unchanged lines hidden --- |