1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/faults.hh"
37#include "arch/alpha/pagetable.hh"
38#include "arch/alpha/tlb.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "cpu/thread_context.hh"
43#include "debug/TLB.hh"
44
45using namespace std;
46

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429 return new ItbAcvFault(req->getVaddr());
430 }
431
432 fetch_hits++;
433 }
434 }
435
436 // check that the physical address is ok (catch bad physical addresses)
437 if (req->getPaddr() & ~PAddrImplMask)
438 return genMachineCheckFault();
439
440 return checkCacheability(req, true);
441
442}
443
444Fault
445TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
446{

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557
558 if (write)
559 write_hits++;
560 else
561 read_hits++;
562 }
563
564 // check that the physical address is ok (catch bad physical addresses)
565 if (req->getPaddr() & ~PAddrImplMask)
566 return genMachineCheckFault();
567
568 return checkCacheability(req);
569}
570
571TlbEntry &
572TLB::index(bool advance)
573{
574 TlbEntry *entry = &table[nlu];

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