1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44
45using namespace std;
46using namespace EV5;
47
48namespace AlphaISA {
49///////////////////////////////////////////////////////////////////////
50//
51// Alpha TLB
52//
53#ifdef DEBUG
54bool uncacheBit39 = false;
55bool uncacheBit40 = false;
56#endif
57
58#define MODE2MASK(X) (1 << (X))
59
60TLB::TLB(const Params *p)
61 : SimObject(p), size(p->size), nlu(0)
62{
63 table = new TlbEntry[size];
64 memset(table, 0, sizeof(TlbEntry[size]));
65 flushCache();
66}
67
68TLB::~TLB()
69{

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279 }
280}
281
282
283///////////////////////////////////////////////////////////////////////
284//
285// Alpha ITB
286//
287ITB::ITB(const Params *p)
288 : TLB(p)
289{}
290
291
292void
293ITB::regStats()
294{
295 hits
296 .name(name() + ".hits")

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393 return checkCacheability(req);
394
395}
396
397///////////////////////////////////////////////////////////////////////
398//
399// Alpha DTB
400//
401 DTB::DTB(const Params *p)
402 : TLB(p)
403{}
404
405void
406DTB::regStats()
407{
408 read_hits
409 .name(name() + ".read_hits")
410 .desc("DTB read hits")

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617 return *entry;
618}
619
620/* end namespace AlphaISA */ }
621
622AlphaISA::ITB *
623AlphaITBParams::create()
624{
625 return new AlphaISA::ITB(this);
626}
627
628AlphaISA::DTB *
629AlphaDTBParams::create()
630{
631 return new AlphaISA::DTB(this);
632}