1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 126 unchanged lines hidden (view full) --- 135#include "base/trace.hh" 136#include "cpu/thread_context.hh" 137#include "cpu/static_inst.hh" 138#include "mem/physical.hh" 139#include "mem/port.hh" 140#include "sim/system.hh" 141 142using namespace std; |
143using namespace AlphaISA; |
144 145RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) 146 : BaseRemoteGDB(_system, c, KGDB_NUMREGS) 147{ 148 memset(gdbregs.regs, 0, gdbregs.bytes()); 149} 150 151/////////////////////////////////////////////////////////// --- 4 unchanged lines hidden (view full) --- 156bool 157RemoteGDB::acc(Addr va, size_t len) 158{ 159#if !FULL_SYSTEM 160 panic("acc function needs to be rewritten for SE mode\n"); 161#else 162 Addr last_va; 163 |
164 va = AlphaISA::TruncPage(va); 165 last_va = AlphaISA::RoundPage(va + len); |
166 167 do { |
168 if (AlphaISA::IsK0Seg(va)) { 169 if (va < (AlphaISA::K0SegBase + pmem->size())) { |
170 DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " 171 "%#x < K0SEG + size\n", va); 172 return true; 173 } else { 174 DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n", 175 va); 176 return false; 177 } --- 5 unchanged lines hidden (view full) --- 183 * accessed physically. At some point this should probably be cleaned up 184 * but there is no easy way to do it. 185 */ 186 187 if (AlphaISA::PcPAL(va) || va < 0x10000) 188 return true; 189 190 Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); |
191 AlphaISA::PageTableEntry pte = AlphaISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); |
192 if (!pte.valid()) { 193 DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); 194 return false; 195 } |
196 va += AlphaISA::PageBytes; |
197 } while (va < last_va); 198 199 DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); 200 return true; 201#endif 202} 203 204/////////////////////////////////////////////////////////// --- 5 unchanged lines hidden (view full) --- 210RemoteGDB::getregs() 211{ 212 memset(gdbregs.regs, 0, gdbregs.bytes()); 213 214 gdbregs.regs[KGDB_REG_PC] = context->readPC(); 215 216 // @todo: Currently this is very Alpha specific. 217 if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { |
218 for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { |
219 gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]); 220 } 221 } else { |
222 for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { |
223 gdbregs.regs[i] = context->readIntReg(i); 224 } 225 } 226 227#ifdef KGDB_FP_REGS |
228 for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) { |
229 gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i); 230 } 231#endif 232} 233 234/////////////////////////////////////////////////////////// 235// RemoteGDB::setregs 236// 237// Translate the GDB register format into the kernel 238// debugger register format. 239// 240void 241RemoteGDB::setregs() 242{ 243 // @todo: Currently this is very Alpha specific. 244 if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { |
245 for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { |
246 context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]); 247 } 248 } else { |
249 for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { |
250 context->setIntReg(i, gdbregs.regs[i]); 251 } 252 } 253 254#ifdef KGDB_FP_REGS |
255 for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) { |
256 context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]); 257 } 258#endif 259 context->setPC(gdbregs.regs[KGDB_REG_PC]); 260} 261 262void 263RemoteGDB::clearSingleStep() --- 54 unchanged lines hidden --- |