registers.hh (13592:b8972ccebd63) | registers.hh (13610:5d5404ac6288) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#ifndef __ARCH_ALPHA_REGISTERS_HH__ 32#define __ARCH_ALPHA_REGISTERS_HH__ 33 34#include "arch/alpha/generated/max_inst_regs.hh" 35#include "arch/alpha/ipr.hh" 36#include "arch/generic/types.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#ifndef __ARCH_ALPHA_REGISTERS_HH__ 32#define __ARCH_ALPHA_REGISTERS_HH__ 33 34#include "arch/alpha/generated/max_inst_regs.hh" 35#include "arch/alpha/ipr.hh" 36#include "arch/generic/types.hh" |
37#include "arch/generic/vec_pred_reg.hh" |
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37#include "arch/generic/vec_reg.hh" 38#include "base/types.hh" 39 40namespace AlphaISA { 41 42using AlphaISAInst::MaxInstSrcRegs; 43using AlphaISAInst::MaxInstDestRegs; 44 --- 6 unchanged lines hidden (view full) --- 51typedef RegVal FloatRegBits; 52 53// control register file contents 54typedef RegVal MiscReg; 55 56// dummy typedef since we don't have CC regs 57typedef uint8_t CCReg; 58 | 38#include "arch/generic/vec_reg.hh" 39#include "base/types.hh" 40 41namespace AlphaISA { 42 43using AlphaISAInst::MaxInstSrcRegs; 44using AlphaISAInst::MaxInstDestRegs; 45 --- 6 unchanged lines hidden (view full) --- 52typedef RegVal FloatRegBits; 53 54// control register file contents 55typedef RegVal MiscReg; 56 57// dummy typedef since we don't have CC regs 58typedef uint8_t CCReg; 59 |
59// dummy typedefs since we don't have vector regs 60constexpr unsigned NumVecElemPerVecReg = 2; 61using VecElem = uint32_t; 62using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 63using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 64using VecRegContainer = VecReg::Container; 65// This has to be one to prevent warnings that are treated as errors 66constexpr unsigned NumVecRegs = 1; | 60// Not applicable to Alpha 61using VecElem = ::DummyVecElem; 62using VecReg = ::DummyVecReg; 63using ConstVecReg = ::DummyConstVecReg; 64using VecRegContainer = ::DummyVecRegContainer; 65constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 66constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; |
67 | 67 |
68// Not applicable to Alpha 69using VecPredReg = ::DummyVecPredReg; 70using ConstVecPredReg = ::DummyConstVecPredReg; 71using VecPredRegContainer = ::DummyVecPredRegContainer; 72constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 73constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 74 |
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68enum MiscRegIndex 69{ 70 MISCREG_FPCR = NumInternalProcRegs, 71 MISCREG_UNIQ, 72 MISCREG_LOCKFLAG, 73 MISCREG_LOCKADDR, 74 MISCREG_INTR, 75 NUM_MISCREGS --- 15 unchanged lines hidden (view full) --- 91const RegIndex SyscallSuccessReg = 19; 92 93const int NumIntArchRegs = 32; 94const int NumPALShadowRegs = 8; 95const int NumFloatArchRegs = 32; 96 97const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 98const int NumFloatRegs = NumFloatArchRegs; | 75enum MiscRegIndex 76{ 77 MISCREG_FPCR = NumInternalProcRegs, 78 MISCREG_UNIQ, 79 MISCREG_LOCKFLAG, 80 MISCREG_LOCKADDR, 81 MISCREG_INTR, 82 NUM_MISCREGS --- 15 unchanged lines hidden (view full) --- 98const RegIndex SyscallSuccessReg = 19; 99 100const int NumIntArchRegs = 32; 101const int NumPALShadowRegs = 8; 102const int NumFloatArchRegs = 32; 103 104const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 105const int NumFloatRegs = NumFloatArchRegs; |
106const int NumVecRegs = 1; // Not applicable to Alpha 107 // (1 to prevent warnings) 108const int NumVecPredRegs = 1; // Not applicable to Alpha 109 // (1 to prevent warnings) |
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99const int NumCCRegs = 0; 100const int NumMiscRegs = NUM_MISCREGS; 101 102const int TotalNumRegs = 103 NumIntRegs + NumFloatRegs + NumMiscRegs; 104 105} // namespace AlphaISA 106 107#endif // __ARCH_ALPHA_REGFILE_HH__ | 110const int NumCCRegs = 0; 111const int NumMiscRegs = NUM_MISCREGS; 112 113const int TotalNumRegs = 114 NumIntRegs + NumFloatRegs + NumMiscRegs; 115 116} // namespace AlphaISA 117 118#endif // __ARCH_ALPHA_REGFILE_HH__ |