registers.hh (12109:f29e9c5418aa) registers.hh (13338:c59f7e47e31d)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 52 unchanged lines hidden (view full) ---

61constexpr unsigned NumVecElemPerVecReg = 2;
62using VecElem = uint32_t;
63using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
64using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
65using VecRegContainer = VecReg::Container;
66// This has to be one to prevent warnings that are treated as errors
67constexpr unsigned NumVecRegs = 1;
68
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 52 unchanged lines hidden (view full) ---

61constexpr unsigned NumVecElemPerVecReg = 2;
62using VecElem = uint32_t;
63using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
64using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
65using VecRegContainer = VecReg::Container;
66// This has to be one to prevent warnings that are treated as errors
67constexpr unsigned NumVecRegs = 1;
68
69union AnyReg
70{
71 IntReg intreg;
72 FloatReg fpreg;
73 MiscReg ctrlreg;
74};
75
76enum MiscRegIndex
77{
78 MISCREG_FPCR = NumInternalProcRegs,
79 MISCREG_UNIQ,
80 MISCREG_LOCKFLAG,
81 MISCREG_LOCKADDR,
82 MISCREG_INTR,
83 NUM_MISCREGS

--- 32 unchanged lines hidden --- 		69enum MiscRegIndex
70{
71 MISCREG_FPCR = NumInternalProcRegs,
72 MISCREG_UNIQ,
73 MISCREG_LOCKFLAG,
74 MISCREG_LOCKADDR,
75 MISCREG_INTR,
76 NUM_MISCREGS

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