registers.hh (10934:5af8f40d8f2c) | registers.hh (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 42 unchanged lines hidden (view full) --- 51typedef uint64_t FloatRegBits; 52 53// control register file contents 54typedef uint64_t MiscReg; 55 56// dummy typedef since we don't have CC regs 57typedef uint8_t CCReg; 58 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 42 unchanged lines hidden (view full) --- 51typedef uint64_t FloatRegBits; 52 53// control register file contents 54typedef uint64_t MiscReg; 55 56// dummy typedef since we don't have CC regs 57typedef uint8_t CCReg; 58 |
59// vector register file entry type 60typedef uint64_t VectorRegElement; 61const int NumVectorRegElements = 0; 62const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); 63typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; 64 | |
65union AnyReg 66{ 67 IntReg intreg; 68 FloatReg fpreg; 69 MiscReg ctrlreg; 70}; 71 72enum MiscRegIndex --- 23 unchanged lines hidden (view full) --- 96 97const int NumIntArchRegs = 32; 98const int NumPALShadowRegs = 8; 99const int NumFloatArchRegs = 32; 100 101const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 102const int NumFloatRegs = NumFloatArchRegs; 103const int NumCCRegs = 0; | 59union AnyReg 60{ 61 IntReg intreg; 62 FloatReg fpreg; 63 MiscReg ctrlreg; 64}; 65 66enum MiscRegIndex --- 23 unchanged lines hidden (view full) --- 90 91const int NumIntArchRegs = 32; 92const int NumPALShadowRegs = 8; 93const int NumFloatArchRegs = 32; 94 95const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 96const int NumFloatRegs = NumFloatArchRegs; 97const int NumCCRegs = 0; |
104const int NumVectorRegs = 0; | |
105const int NumMiscRegs = NUM_MISCREGS; 106 107const int TotalNumRegs = 108 NumIntRegs + NumFloatRegs + NumMiscRegs; 109 110// These enumerate all the registers for dependence tracking. 111enum DependenceTags { 112 // 0..31 are the integer regs 0..31 113 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) 114 FP_Reg_Base = NumIntRegs, 115 CC_Reg_Base = FP_Reg_Base + NumFloatRegs, | 98const int NumMiscRegs = NUM_MISCREGS; 99 100const int TotalNumRegs = 101 NumIntRegs + NumFloatRegs + NumMiscRegs; 102 103// These enumerate all the registers for dependence tracking. 104enum DependenceTags { 105 // 0..31 are the integer regs 0..31 106 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) 107 FP_Reg_Base = NumIntRegs, 108 CC_Reg_Base = FP_Reg_Base + NumFloatRegs, |
116 Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 117 Misc_Reg_Base = Vector_Reg_Base + NumCCRegs, // NumVectorRegs == 0 | 109 Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 |
118 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs 119}; 120 121} // namespace AlphaISA 122 123#endif // __ARCH_ALPHA_REGFILE_HH__ | 110 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs 111}; 112 113} // namespace AlphaISA 114 115#endif // __ARCH_ALPHA_REGFILE_HH__ |