process.cc (7678:f19b6a3a8cec) process.cc (7701:324323fe947b)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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200
201 LiveProcess::initState();
202
203 argsInit(MachineBytes, VMPageSize);
204
205 ThreadContext *tc = system->getThreadContext(contextIds[0]);
206 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
207 //Operate in user mode
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 191 unchanged lines hidden (view full) ---

200
201 LiveProcess::initState();
202
203 argsInit(MachineBytes, VMPageSize);
204
205 ThreadContext *tc = system->getThreadContext(contextIds[0]);
206 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
207 //Operate in user mode
208 tc->setMiscRegNoEffect(IPR_ICM, 0x18);
208 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
209 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
209 //No super page mapping
210 tc->setMiscRegNoEffect(IPR_MCSR, 0);
211}
212
213AlphaISA::IntReg
214AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
215{
216 assert(i < 6);

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210 //No super page mapping
211 tc->setMiscRegNoEffect(IPR_MCSR, 0);
212}
213
214AlphaISA::IntReg
215AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
216{
217 assert(i < 6);

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