process.cc (6227:a17798f2a52c) process.cc (6701:4842482e1bd1)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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188 tc->setMiscRegNoEffect(IPR_ICM, 0x18);
189 //No super page mapping
190 tc->setMiscRegNoEffect(IPR_MCSR, 0);
191 //Set this to 0 for now, but it should be unique for each process
192 tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
193}
194
195AlphaISA::IntReg
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 179 unchanged lines hidden (view full) ---

188 tc->setMiscRegNoEffect(IPR_ICM, 0x18);
189 //No super page mapping
190 tc->setMiscRegNoEffect(IPR_MCSR, 0);
191 //Set this to 0 for now, but it should be unique for each process
192 tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
193}
194
195AlphaISA::IntReg
196AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int i)
196AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
197{
198 assert(i < 6);
197{
198 assert(i < 6);
199 return tc->readIntReg(FirstArgumentReg + i);
199 return tc->readIntReg(FirstArgumentReg + i++);
200}
201
202void
203AlphaLiveProcess::setSyscallArg(ThreadContext *tc,
204 int i, AlphaISA::IntReg val)
205{
206 assert(i < 6);
207 tc->setIntReg(FirstArgumentReg + i, val);

--- 19 unchanged lines hidden --- 		200}
201
202void
203AlphaLiveProcess::setSyscallArg(ThreadContext *tc,
204 int i, AlphaISA::IntReg val)
205{
206 assert(i < 6);
207 tc->setIntReg(FirstArgumentReg + i, val);

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