process.cc (6110:5051aafec8d5) process.cc (6180:1a8950d566ff)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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161 setSyscallArg(tc, 0, argc);
162 setSyscallArg(tc, 1, argv_array_base);
163 tc->setIntReg(StackPointerReg, stack_min);
164
165 Addr prog_entry = objFile->entryPoint();
166 tc->setPC(prog_entry);
167 tc->setNextPC(prog_entry + sizeof(MachInst));
168
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 152 unchanged lines hidden (view full) ---

161 setSyscallArg(tc, 0, argc);
162 setSyscallArg(tc, 1, argv_array_base);
163 tc->setIntReg(StackPointerReg, stack_min);
164
165 Addr prog_entry = objFile->entryPoint();
166 tc->setPC(prog_entry);
167 tc->setNextPC(prog_entry + sizeof(MachInst));
168
169#if THE_ISA != ALPHA_ISA //e.g. MIPS or Sparc
169 // MIPS/Sparc need NNPC for delay slot handling, while
170 // Alpha has no delay slots... However, CPU models
171 // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this
172 // here ensures CPU-Model Compatibility across board
170 tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
173 tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
171#endif
172
173
174}
175
176void
177AlphaLiveProcess::startup()
178{
179 if (checkpointRestored)
180 return;
181

--- 46 unchanged lines hidden --- 		174}
175
176void
177AlphaLiveProcess::startup()
178{
179 if (checkpointRestored)
180 return;
181

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