process.cc (13028:9a09c342891e) | process.cc (13614:52c5311db96b) |
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1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 208 unchanged lines hidden (view full) --- 217 tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 218 //Operate in user mode 219 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 220 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 221 //No super page mapping 222 tc->setMiscRegNoEffect(IPR_MCSR, 0); 223} 224 | 1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 208 unchanged lines hidden (view full) --- 217 tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 218 //Operate in user mode 219 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 220 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 221 //No super page mapping 222 tc->setMiscRegNoEffect(IPR_MCSR, 0); 223} 224 |
225AlphaISA::IntReg | 225RegVal |
226AlphaProcess::getSyscallArg(ThreadContext *tc, int &i) 227{ 228 assert(i < 6); 229 return tc->readIntReg(FirstArgumentReg + i++); 230} 231 232void | 226AlphaProcess::getSyscallArg(ThreadContext *tc, int &i) 227{ 228 assert(i < 6); 229 return tc->readIntReg(FirstArgumentReg + i++); 230} 231 232void |
233AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) | 233AlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) |
234{ 235 assert(i < 6); 236 tc->setIntReg(FirstArgumentReg + i, val); 237} 238 239void 240AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 241{ 242 // check for error condition. Alpha syscall convention is to 243 // indicate success/failure in reg a3 (r19) and put the 244 // return value itself in the standard return value reg (v0). 245 if (sysret.successful()) { 246 // no error 247 tc->setIntReg(SyscallSuccessReg, 0); 248 tc->setIntReg(ReturnValueReg, sysret.returnValue()); 249 } else { 250 // got an error, return details | 234{ 235 assert(i < 6); 236 tc->setIntReg(FirstArgumentReg + i, val); 237} 238 239void 240AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 241{ 242 // check for error condition. Alpha syscall convention is to 243 // indicate success/failure in reg a3 (r19) and put the 244 // return value itself in the standard return value reg (v0). 245 if (sysret.successful()) { 246 // no error 247 tc->setIntReg(SyscallSuccessReg, 0); 248 tc->setIntReg(ReturnValueReg, sysret.returnValue()); 249 } else { 250 // got an error, return details |
251 tc->setIntReg(SyscallSuccessReg, (IntReg)-1); | 251 tc->setIntReg(SyscallSuccessReg, (RegVal)-1); |
252 tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 253 } 254} | 252 tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 253 } 254} |