process.cc (11801:cd7f3a1dbf55) | process.cc (11851:824055fe6b30) |
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1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "sim/byteswap.hh" 42#include "sim/process_impl.hh" 43#include "sim/syscall_return.hh" 44#include "sim/system.hh" 45 46using namespace AlphaISA; 47using namespace std; 48 | 1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "sim/byteswap.hh" 42#include "sim/process_impl.hh" 43#include "sim/syscall_return.hh" 44#include "sim/system.hh" 45 46using namespace AlphaISA; 47using namespace std; 48 |
49AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 50 ObjectFile *objFile) 51 : LiveProcess(params, objFile) | 49AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile) 50 : Process(params, objFile) |
52{ 53 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 54 brk_point = roundUp(brk_point, PageBytes); 55 56 // Set up stack. On Alpha, stack goes below text section. This 57 // code should get moved to some architecture-specific spot. 58 stack_base = objFile->textBase() - (409600+4096); 59 60 // Set up region for mmaps. Tru64 seems to start just above 0 and 61 // grow up from there. 62 mmap_end = 0x10000; 63 64 // Set pointer for next thread stack. Reserve 8M for main stack. 65 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 66 67} 68 69void | 51{ 52 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 53 brk_point = roundUp(brk_point, PageBytes); 54 55 // Set up stack. On Alpha, stack goes below text section. This 56 // code should get moved to some architecture-specific spot. 57 stack_base = objFile->textBase() - (409600+4096); 58 59 // Set up region for mmaps. Tru64 seems to start just above 0 and 60 // grow up from there. 61 mmap_end = 0x10000; 62 63 // Set pointer for next thread stack. Reserve 8M for main stack. 64 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 65 66} 67 68void |
70AlphaLiveProcess::argsInit(int intSize, int pageSize) | 69AlphaProcess::argsInit(int intSize, int pageSize) |
71{ 72 // Patch the ld_bias for dynamic executables. 73 updateBias(); 74 75 objFile->loadSections(initVirtMem); 76 77 typedef AuxVector<uint64_t> auxv_t; 78 std::vector<auxv_t> auxv; --- 92 unchanged lines hidden (view full) --- 171 setSyscallArg(tc, 0, argc); 172 setSyscallArg(tc, 1, argv_array_base); 173 tc->setIntReg(StackPointerReg, stack_min); 174 175 tc->pcState(getStartPC()); 176} 177 178void | 70{ 71 // Patch the ld_bias for dynamic executables. 72 updateBias(); 73 74 objFile->loadSections(initVirtMem); 75 76 typedef AuxVector<uint64_t> auxv_t; 77 std::vector<auxv_t> auxv; --- 92 unchanged lines hidden (view full) --- 170 setSyscallArg(tc, 0, argc); 171 setSyscallArg(tc, 1, argv_array_base); 172 tc->setIntReg(StackPointerReg, stack_min); 173 174 tc->pcState(getStartPC()); 175} 176 177void |
179AlphaLiveProcess::setupASNReg() | 178AlphaProcess::setupASNReg() |
180{ 181 ThreadContext *tc = system->getThreadContext(contextIds[0]); 182 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57); 183} 184 185 186void | 179{ 180 ThreadContext *tc = system->getThreadContext(contextIds[0]); 181 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57); 182} 183 184 185void |
187AlphaLiveProcess::loadState(CheckpointIn &cp) | 186AlphaProcess::loadState(CheckpointIn &cp) |
188{ | 187{ |
189 LiveProcess::loadState(cp); | 188 Process::loadState(cp); |
190 // need to set up ASN after unserialization since _pid value may 191 // come from checkpoint 192 setupASNReg(); 193} 194 195 196void | 189 // need to set up ASN after unserialization since _pid value may 190 // come from checkpoint 191 setupASNReg(); 192} 193 194 195void |
197AlphaLiveProcess::initState() | 196AlphaProcess::initState() |
198{ 199 // need to set up ASN before further initialization since init 200 // will involve writing to virtual memory addresses 201 setupASNReg(); 202 | 197{ 198 // need to set up ASN before further initialization since init 199 // will involve writing to virtual memory addresses 200 setupASNReg(); 201 |
203 LiveProcess::initState(); | 202 Process::initState(); |
204 205 argsInit(MachineBytes, PageBytes); 206 207 ThreadContext *tc = system->getThreadContext(contextIds[0]); 208 tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 209 //Operate in user mode 210 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 211 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 212 //No super page mapping 213 tc->setMiscRegNoEffect(IPR_MCSR, 0); 214} 215 216AlphaISA::IntReg | 203 204 argsInit(MachineBytes, PageBytes); 205 206 ThreadContext *tc = system->getThreadContext(contextIds[0]); 207 tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 208 //Operate in user mode 209 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 210 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 211 //No super page mapping 212 tc->setMiscRegNoEffect(IPR_MCSR, 0); 213} 214 215AlphaISA::IntReg |
217AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i) | 216AlphaProcess::getSyscallArg(ThreadContext *tc, int &i) |
218{ 219 assert(i < 6); 220 return tc->readIntReg(FirstArgumentReg + i++); 221} 222 223void | 217{ 218 assert(i < 6); 219 return tc->readIntReg(FirstArgumentReg + i++); 220} 221 222void |
224AlphaLiveProcess::setSyscallArg(ThreadContext *tc, 225 int i, AlphaISA::IntReg val) | 223AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) |
226{ 227 assert(i < 6); 228 tc->setIntReg(FirstArgumentReg + i, val); 229} 230 231void | 224{ 225 assert(i < 6); 226 tc->setIntReg(FirstArgumentReg + i, val); 227} 228 229void |
232AlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) | 230AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) |
233{ 234 // check for error condition. Alpha syscall convention is to 235 // indicate success/failure in reg a3 (r19) and put the 236 // return value itself in the standard return value reg (v0). 237 if (sysret.successful()) { 238 // no error 239 tc->setIntReg(SyscallSuccessReg, 0); 240 tc->setIntReg(ReturnValueReg, sysret.returnValue()); 241 } else { 242 // got an error, return details 243 tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 244 tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 245 } 246} | 231{ 232 // check for error condition. Alpha syscall convention is to 233 // indicate success/failure in reg a3 (r19) and put the 234 // return value itself in the standard return value reg (v0). 235 if (sysret.successful()) { 236 // no error 237 tc->setIntReg(SyscallSuccessReg, 0); 238 tc->setIntReg(ReturnValueReg, sysret.returnValue()); 239 } else { 240 // got an error, return details 241 tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 242 tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 243 } 244} |