1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 32 unchanged lines hidden (view full) ---

41#include "sim/byteswap.hh"
42#include "sim/process_impl.hh"
43#include "sim/syscall_return.hh"
44#include "sim/system.hh"
45
46using namespace AlphaISA;
47using namespace std;
48
49AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params,
50 ObjectFile *objFile)
51 : LiveProcess(params, objFile)
49AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
50 : Process(params, objFile)
51{
52 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
53 brk_point = roundUp(brk_point, PageBytes);
54
55 // Set up stack. On Alpha, stack goes below text section. This
56 // code should get moved to some architecture-specific spot.
57 stack_base = objFile->textBase() - (409600+4096);
58
59 // Set up region for mmaps. Tru64 seems to start just above 0 and
60 // grow up from there.
61 mmap_end = 0x10000;
62
63 // Set pointer for next thread stack. Reserve 8M for main stack.
64 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
65
66}
67
68void
70AlphaLiveProcess::argsInit(int intSize, int pageSize)
69AlphaProcess::argsInit(int intSize, int pageSize)
70{
71 // Patch the ld_bias for dynamic executables.
72 updateBias();
73
74 objFile->loadSections(initVirtMem);
75
76 typedef AuxVector<uint64_t> auxv_t;
77 std::vector<auxv_t> auxv;

--- 92 unchanged lines hidden (view full) ---

170 setSyscallArg(tc, 0, argc);
171 setSyscallArg(tc, 1, argv_array_base);
172 tc->setIntReg(StackPointerReg, stack_min);
173
174 tc->pcState(getStartPC());
175}
176
177void
179AlphaLiveProcess::setupASNReg()
178AlphaProcess::setupASNReg()
179{
180 ThreadContext *tc = system->getThreadContext(contextIds[0]);
181 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
182}
183
184
185void
187AlphaLiveProcess::loadState(CheckpointIn &cp)
186AlphaProcess::loadState(CheckpointIn &cp)
187{
189 LiveProcess::loadState(cp);
188 Process::loadState(cp);
189 // need to set up ASN after unserialization since _pid value may
190 // come from checkpoint
191 setupASNReg();
192}
193
194
195void
197AlphaLiveProcess::initState()
196AlphaProcess::initState()
197{
198 // need to set up ASN before further initialization since init
199 // will involve writing to virtual memory addresses
200 setupASNReg();
201
203 LiveProcess::initState();
202 Process::initState();
203
204 argsInit(MachineBytes, PageBytes);
205
206 ThreadContext *tc = system->getThreadContext(contextIds[0]);
207 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
208 //Operate in user mode
209 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
210 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
211 //No super page mapping
212 tc->setMiscRegNoEffect(IPR_MCSR, 0);
213}
214
215AlphaISA::IntReg
217AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
216AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
217{
218 assert(i < 6);
219 return tc->readIntReg(FirstArgumentReg + i++);
220}
221
222void
224AlphaLiveProcess::setSyscallArg(ThreadContext *tc,
225 int i, AlphaISA::IntReg val)
223AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
224{
225 assert(i < 6);
226 tc->setIntReg(FirstArgumentReg + i, val);
227}
228
229void
232AlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
230AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
231{
232 // check for error condition. Alpha syscall convention is to
233 // indicate success/failure in reg a3 (r19) and put the
234 // return value itself in the standard return value reg (v0).
235 if (sysret.successful()) {
236 // no error
237 tc->setIntReg(SyscallSuccessReg, 0);
238 tc->setIntReg(ReturnValueReg, sysret.returnValue());
239 } else {
240 // got an error, return details
241 tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
242 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
243 }
244}