1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/alpha/process.hh"
33
34#include "arch/alpha/isa_traits.hh"
35#include "base/loader/elf_object.hh"
36#include "base/loader/object_file.hh"
37#include "base/misc.hh"
38#include "cpu/thread_context.hh"
39#include "debug/Loader.hh"
40#include "mem/page_table.hh"
41#include "sim/aux_vector.hh"
42#include "sim/byteswap.hh"
43#include "sim/process_impl.hh"
44#include "sim/syscall_return.hh"
45#include "sim/system.hh"
46
47using namespace AlphaISA;
48using namespace std;
49
50AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
51 : Process(params, objFile)
52{
| 1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/alpha/process.hh"
33
34#include "arch/alpha/isa_traits.hh"
35#include "base/loader/elf_object.hh"
36#include "base/loader/object_file.hh"
37#include "base/misc.hh"
38#include "cpu/thread_context.hh"
39#include "debug/Loader.hh"
40#include "mem/page_table.hh"
41#include "sim/aux_vector.hh"
42#include "sim/byteswap.hh"
43#include "sim/process_impl.hh"
44#include "sim/syscall_return.hh"
45#include "sim/system.hh"
46
47using namespace AlphaISA;
48using namespace std;
49
50AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
51 : Process(params, objFile)
52{
|
53 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
54 brk_point = roundUp(brk_point, PageBytes);
| 53 memState->brkPoint = objFile->dataBase() + objFile->dataSize() +
54 objFile->bssSize();
55 memState->brkPoint = roundUp(memState->brkPoint, PageBytes);
|
55
56 // Set up stack. On Alpha, stack goes below text section. This
57 // code should get moved to some architecture-specific spot.
| 56
57 // Set up stack. On Alpha, stack goes below text section. This
58 // code should get moved to some architecture-specific spot.
|
58 stack_base = objFile->textBase() - (409600+4096);
| 59 memState->stackBase = objFile->textBase() - (409600+4096);
|
59
60 // Set up region for mmaps. Tru64 seems to start just above 0 and
61 // grow up from there.
| 60
61 // Set up region for mmaps. Tru64 seems to start just above 0 and
62 // grow up from there.
|
62 mmap_end = 0x10000;
| 63 memState->mmapEnd = 0x10000;
|
63
64 // Set pointer for next thread stack. Reserve 8M for main stack.
| 64
65 // Set pointer for next thread stack. Reserve 8M for main stack.
|
65 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
| 66 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
|
66
67}
68
69void
70AlphaProcess::argsInit(int intSize, int pageSize)
71{
72 // Patch the ld_bias for dynamic executables.
73 updateBias();
74
75 objFile->loadSections(initVirtMem);
76
77 typedef AuxVector<uint64_t> auxv_t;
78 std::vector<auxv_t> auxv;
79
80 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
81 if (elfObject)
82 {
83 // modern glibc uses a bunch of auxiliary vectors to set up
84 // TLS as well as do a bunch of other stuff
85 // these vectors go on the bottom of the stack, below argc/argv/envp
86 // pointers but above actual arg strings
87 // I don't have all the ones glibc looks at here, but so far it doesn't
88 // seem to be a problem.
89 // check out _dl_aux_init() in glibc/elf/dl-support.c for details
90 // --Lisa
91 auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
92 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
93 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
94 DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
95 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
96 // This is the base address of the ELF interpreter; it should be
97 // zero for static executables or contain the base address for
98 // dynamic executables.
99 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
100 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
101 auxv.push_back(auxv_t(M5_AT_UID, uid()));
102 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
103 auxv.push_back(auxv_t(M5_AT_GID, gid()));
104 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
105
106 }
107
108 // Calculate how much space we need for arg & env & auxv arrays.
109 int argv_array_size = intSize * (argv.size() + 1);
110 int envp_array_size = intSize * (envp.size() + 1);
111 int auxv_array_size = intSize * 2 * (auxv.size() + 1);
112
113 int arg_data_size = 0;
114 for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
115 arg_data_size += argv[i].size() + 1;
116 }
117 int env_data_size = 0;
118 for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
119 env_data_size += envp[i].size() + 1;
120 }
121
122 int space_needed =
123 argv_array_size +
124 envp_array_size +
125 auxv_array_size +
126 arg_data_size +
127 env_data_size;
128
129 if (space_needed < 32*1024)
130 space_needed = 32*1024;
131
132 // set bottom of stack
| 67
68}
69
70void
71AlphaProcess::argsInit(int intSize, int pageSize)
72{
73 // Patch the ld_bias for dynamic executables.
74 updateBias();
75
76 objFile->loadSections(initVirtMem);
77
78 typedef AuxVector<uint64_t> auxv_t;
79 std::vector<auxv_t> auxv;
80
81 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
82 if (elfObject)
83 {
84 // modern glibc uses a bunch of auxiliary vectors to set up
85 // TLS as well as do a bunch of other stuff
86 // these vectors go on the bottom of the stack, below argc/argv/envp
87 // pointers but above actual arg strings
88 // I don't have all the ones glibc looks at here, but so far it doesn't
89 // seem to be a problem.
90 // check out _dl_aux_init() in glibc/elf/dl-support.c for details
91 // --Lisa
92 auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
93 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
94 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
95 DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
96 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
97 // This is the base address of the ELF interpreter; it should be
98 // zero for static executables or contain the base address for
99 // dynamic executables.
100 auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
101 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
102 auxv.push_back(auxv_t(M5_AT_UID, uid()));
103 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
104 auxv.push_back(auxv_t(M5_AT_GID, gid()));
105 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
106
107 }
108
109 // Calculate how much space we need for arg & env & auxv arrays.
110 int argv_array_size = intSize * (argv.size() + 1);
111 int envp_array_size = intSize * (envp.size() + 1);
112 int auxv_array_size = intSize * 2 * (auxv.size() + 1);
113
114 int arg_data_size = 0;
115 for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
116 arg_data_size += argv[i].size() + 1;
117 }
118 int env_data_size = 0;
119 for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
120 env_data_size += envp[i].size() + 1;
121 }
122
123 int space_needed =
124 argv_array_size +
125 envp_array_size +
126 auxv_array_size +
127 arg_data_size +
128 env_data_size;
129
130 if (space_needed < 32*1024)
131 space_needed = 32*1024;
132
133 // set bottom of stack
|
133 stack_min = stack_base - space_needed;
| 134 memState->stackMin = memState->stackBase - space_needed;
|
134 // align it
| 135 // align it
|
135 stack_min = roundDown(stack_min, pageSize);
136 stack_size = stack_base - stack_min;
| 136 memState->stackMin = roundDown(memState->stackMin, pageSize);
137 memState->stackSize = memState->stackBase - memState->stackMin;
|
137 // map memory
| 138 // map memory
|
138 allocateMem(stack_min, roundUp(stack_size, pageSize));
| 139 allocateMem(memState->stackMin, roundUp(memState->stackSize, pageSize));
|
139
140 // map out initial stack contents
| 140
141 // map out initial stack contents
|
141 Addr argv_array_base = stack_min + intSize; // room for argc
| 142 Addr argv_array_base = memState->stackMin + intSize; // room for argc
|
142 Addr envp_array_base = argv_array_base + argv_array_size;
143 Addr auxv_array_base = envp_array_base + envp_array_size;
144 Addr arg_data_base = auxv_array_base + auxv_array_size;
145 Addr env_data_base = arg_data_base + arg_data_size;
146
147 // write contents to stack
148 uint64_t argc = argv.size();
149 if (intSize == 8)
150 argc = htog((uint64_t)argc);
151 else if (intSize == 4)
152 argc = htog((uint32_t)argc);
153 else
154 panic("Unknown int size");
155
| 143 Addr envp_array_base = argv_array_base + argv_array_size;
144 Addr auxv_array_base = envp_array_base + envp_array_size;
145 Addr arg_data_base = auxv_array_base + auxv_array_size;
146 Addr env_data_base = arg_data_base + arg_data_size;
147
148 // write contents to stack
149 uint64_t argc = argv.size();
150 if (intSize == 8)
151 argc = htog((uint64_t)argc);
152 else if (intSize == 4)
153 argc = htog((uint32_t)argc);
154 else
155 panic("Unknown int size");
156
|
156 initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize);
| 157 initVirtMem.writeBlob(memState->stackMin, (uint8_t*)&argc, intSize);
|
157
158 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
159 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
160
161 //Copy the aux stuff
162 for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
163 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
164 (uint8_t*)&(auxv[x].a_type), intSize);
165 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
166 (uint8_t*)&(auxv[x].a_val), intSize);
167 }
168
169 ThreadContext *tc = system->getThreadContext(contextIds[0]);
170
171 setSyscallArg(tc, 0, argc);
172 setSyscallArg(tc, 1, argv_array_base);
| 158
159 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
160 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
161
162 //Copy the aux stuff
163 for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
164 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
165 (uint8_t*)&(auxv[x].a_type), intSize);
166 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
167 (uint8_t*)&(auxv[x].a_val), intSize);
168 }
169
170 ThreadContext *tc = system->getThreadContext(contextIds[0]);
171
172 setSyscallArg(tc, 0, argc);
173 setSyscallArg(tc, 1, argv_array_base);
|
173 tc->setIntReg(StackPointerReg, stack_min);
| 174 tc->setIntReg(StackPointerReg, memState->stackMin);
|
174
175 tc->pcState(getStartPC());
176}
177
178void
179AlphaProcess::setupASNReg()
180{
181 ThreadContext *tc = system->getThreadContext(contextIds[0]);
182 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
183}
184
185
186void
187AlphaProcess::loadState(CheckpointIn &cp)
188{
189 Process::loadState(cp);
190 // need to set up ASN after unserialization since _pid value may
191 // come from checkpoint
192 setupASNReg();
193}
194
195
196void
197AlphaProcess::initState()
198{
199 // need to set up ASN before further initialization since init
200 // will involve writing to virtual memory addresses
201 setupASNReg();
202
203 Process::initState();
204
205 argsInit(MachineBytes, PageBytes);
206
207 ThreadContext *tc = system->getThreadContext(contextIds[0]);
208 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
209 //Operate in user mode
210 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
211 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
212 //No super page mapping
213 tc->setMiscRegNoEffect(IPR_MCSR, 0);
214}
215
216AlphaISA::IntReg
217AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
218{
219 assert(i < 6);
220 return tc->readIntReg(FirstArgumentReg + i++);
221}
222
223void
224AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
225{
226 assert(i < 6);
227 tc->setIntReg(FirstArgumentReg + i, val);
228}
229
230void
231AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
232{
233 // check for error condition. Alpha syscall convention is to
234 // indicate success/failure in reg a3 (r19) and put the
235 // return value itself in the standard return value reg (v0).
236 if (sysret.successful()) {
237 // no error
238 tc->setIntReg(SyscallSuccessReg, 0);
239 tc->setIntReg(ReturnValueReg, sysret.returnValue());
240 } else {
241 // got an error, return details
242 tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
243 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
244 }
245}
| 175
176 tc->pcState(getStartPC());
177}
178
179void
180AlphaProcess::setupASNReg()
181{
182 ThreadContext *tc = system->getThreadContext(contextIds[0]);
183 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
184}
185
186
187void
188AlphaProcess::loadState(CheckpointIn &cp)
189{
190 Process::loadState(cp);
191 // need to set up ASN after unserialization since _pid value may
192 // come from checkpoint
193 setupASNReg();
194}
195
196
197void
198AlphaProcess::initState()
199{
200 // need to set up ASN before further initialization since init
201 // will involve writing to virtual memory addresses
202 setupASNReg();
203
204 Process::initState();
205
206 argsInit(MachineBytes, PageBytes);
207
208 ThreadContext *tc = system->getThreadContext(contextIds[0]);
209 tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
210 //Operate in user mode
211 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
212 tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
213 //No super page mapping
214 tc->setMiscRegNoEffect(IPR_MCSR, 0);
215}
216
217AlphaISA::IntReg
218AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
219{
220 assert(i < 6);
221 return tc->readIntReg(FirstArgumentReg + i++);
222}
223
224void
225AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
226{
227 assert(i < 6);
228 tc->setIntReg(FirstArgumentReg + i, val);
229}
230
231void
232AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
233{
234 // check for error condition. Alpha syscall convention is to
235 // indicate success/failure in reg a3 (r19) and put the
236 // return value itself in the standard return value reg (v0).
237 if (sysret.successful()) {
238 // no error
239 tc->setIntReg(SyscallSuccessReg, 0);
240 tc->setIntReg(ReturnValueReg, sysret.returnValue());
241 } else {
242 // got an error, return details
243 tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
244 tc->setIntReg(ReturnValueReg, sysret.errnoValue());
245 }
246}
|