mmapped_ipr.hh (9180:ee8d7a51651d) mmapped_ipr.hh (9897:e105fbf799e7)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#define __ARCH_ALPHA_MMAPPED_IPR_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for memory mapped IPR accesses.
38 */
39
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#define __ARCH_ALPHA_MMAPPED_IPR_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for memory mapped IPR accesses.
38 */
39
40#include "base/types.hh"
41#include "mem/packet.hh"
40#include "arch/generic/mmapped_ipr.hh"
42
41
43class ThreadContext;
44
45namespace AlphaISA {
42namespace AlphaISA {
46
47inline Cycles
48handleIprRead(ThreadContext *xc, Packet *pkt)
49{
50 panic("No handleIprRead implementation in Alpha\n");
51}
52
53
54inline Cycles
55handleIprWrite(ThreadContext *xc, Packet *pkt)
56{
57 panic("No handleIprWrite implementation in Alpha\n");
58}
59
60
43 using GenericISA::handleIprRead;
44 using GenericISA::handleIprWrite;
61} // namespace AlphaISA
62
63#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__
45} // namespace AlphaISA
46
47#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__