locked_mem.hh (6330:786136379872) locked_mem.hh (7783:9b880b40ac10)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50#include "mem/request.hh"
51
52namespace AlphaISA {
53
54template <class XC>
55inline void
56handleLockedRead(XC *xc, Request *req)
57{
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50#include "mem/request.hh"
51
52namespace AlphaISA {
53
54template <class XC>
55inline void
56handleLockedRead(XC *xc, Request *req)
57{
58 xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
59 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
58 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
59 xc->setMiscReg(MISCREG_LOCKFLAG, true);
60}
61
62
63template <class XC>
64inline bool
65handleLockedWrite(XC *xc, Request *req)
66{
67 if (req->isUncacheable()) {
68 // Funky Turbolaser mailbox access...don't update
69 // result register (see stq_c in decoder.isa)
70 req->setExtraData(2);
71 } else {
72 // standard store conditional
60}
61
62
63template <class XC>
64inline bool
65handleLockedWrite(XC *xc, Request *req)
66{
67 if (req->isUncacheable()) {
68 // Funky Turbolaser mailbox access...don't update
69 // result register (see stq_c in decoder.isa)
70 req->setExtraData(2);
71 } else {
72 // standard store conditional
73 bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
74 Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
73 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
74 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
75 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
76 // Lock flag not set or addr mismatch in CPU;
77 // don't even bother sending to memory system
78 req->setExtraData(0);
75 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
76 // Lock flag not set or addr mismatch in CPU;
77 // don't even bother sending to memory system
78 req->setExtraData(0);
79 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
79 xc->setMiscReg(MISCREG_LOCKFLAG, false);
80 // the rest of this code is not architectural;
81 // it's just a debugging aid to help detect
82 // livelock by warning on long sequences of failed
83 // store conditionals
84 int stCondFailures = xc->readStCondFailures();
85 stCondFailures++;
86 xc->setStCondFailures(stCondFailures);
87 if (stCondFailures % 100000 == 0) {

--- 16 unchanged lines hidden --- 		80 // the rest of this code is not architectural;
81 // it's just a debugging aid to help detect
82 // livelock by warning on long sequences of failed
83 // store conditionals
84 int stCondFailures = xc->readStCondFailures();
85 stCondFailures++;
86 xc->setStCondFailures(stCondFailures);
87 if (stCondFailures % 100000 == 0) {

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