locked_mem.hh (4050:cf1daaef9109) locked_mem.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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51
52
53namespace AlphaISA
54{
55template <class XC>
56inline void
57handleLockedRead(XC *xc, Request *req)
58{
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 42 unchanged lines hidden (view full) ---

51
52
53namespace AlphaISA
54{
55template <class XC>
56inline void
57handleLockedRead(XC *xc, Request *req)
58{
59 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
60 xc->setMiscReg(MISCREG_LOCKFLAG, true);
59 xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
60 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
61}
62
63
64template <class XC>
65inline bool
66handleLockedWrite(XC *xc, Request *req)
67{
68 if (req->isUncacheable()) {
69 // Funky Turbolaser mailbox access...don't update
70 // result register (see stq_c in decoder.isa)
71 req->setExtraData(2);
72 } else {
73 // standard store conditional
61}
62
63
64template <class XC>
65inline bool
66handleLockedWrite(XC *xc, Request *req)
67{
68 if (req->isUncacheable()) {
69 // Funky Turbolaser mailbox access...don't update
70 // result register (see stq_c in decoder.isa)
71 req->setExtraData(2);
72 } else {
73 // standard store conditional
74 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
75 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
74 bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
75 Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
76 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
77 // Lock flag not set or addr mismatch in CPU;
78 // don't even bother sending to memory system
79 req->setExtraData(0);
76 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
77 // Lock flag not set or addr mismatch in CPU;
78 // don't even bother sending to memory system
79 req->setExtraData(0);
80 xc->setMiscReg(MISCREG_LOCKFLAG, false);
80 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);
88 if (stCondFailures % 100000 == 0) {

--- 17 unchanged lines hidden --- 		81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);
88 if (stCondFailures % 100000 == 0) {

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