locked_mem.hh (4027:53292b42ee1c) locked_mem.hh (4040:eb894f3fc168)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
32#define __ARCH_ALPHA_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
32#define __ARCH_ALPHA_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 *
39 * Note that these functions are not embedded in the ISA description
40 * because they operate on the *physical* address rather than the
41 * virtual address. In the current M5 design, the physical address is
42 * not accessible from the ISA description, only from the CPU model.
43 * Thus the CPU is responsible for calling back to the ISA (here)
44 * after the address translation has been performed to allow the ISA
45 * to do these manipulations based on the physical address.
46 */
47
48#include "arch/alpha/miscregfile.hh"
49#include "base/misc.hh"
50#include "mem/request.hh"
51
52
53namespace AlphaISA

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63
64template <class XC>
65inline bool
66handleLockedWrite(XC *xc, Request *req)
67{
68 if (req->isUncacheable()) {
69 // Funky Turbolaser mailbox access...don't update
70 // result register (see stq_c in decoder.isa)
38 */
39
40#include "arch/alpha/miscregfile.hh"
41#include "base/misc.hh"
42#include "mem/request.hh"
43
44
45namespace AlphaISA

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55
56template <class XC>
57inline bool
58handleLockedWrite(XC *xc, Request *req)
59{
60 if (req->isUncacheable()) {
61 // Funky Turbolaser mailbox access...don't update
62 // result register (see stq_c in decoder.isa)
71 req->setScResult(2);
63 req->setExtraData(2);
72 } else {
73 // standard store conditional
74 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
75 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
76 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
77 // Lock flag not set or addr mismatch in CPU;
78 // don't even bother sending to memory system
64 } else {
65 // standard store conditional
66 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
67 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
68 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
69 // Lock flag not set or addr mismatch in CPU;
70 // don't even bother sending to memory system
79 req->setScResult(0);
71 req->setExtraData(0);
80 xc->setMiscReg(MISCREG_LOCKFLAG, false);
81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);

--- 18 unchanged lines hidden --- 		72 xc->setMiscReg(MISCREG_LOCKFLAG, false);
73 // the rest of this code is not architectural;
74 // it's just a debugging aid to help detect
75 // livelock by warning on long sequences of failed
76 // store conditionals
77 int stCondFailures = xc->readStCondFailures();
78 stCondFailures++;
79 xc->setStCondFailures(stCondFailures);

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