1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 71 unchanged lines hidden (view full) --- 80 // the rest of this code is not architectural; 81 // it's just a debugging aid to help detect 82 // livelock by warning on long sequences of failed 83 // store conditionals 84 int stCondFailures = xc->readStCondFailures(); 85 stCondFailures++; 86 xc->setStCondFailures(stCondFailures); 87 if (stCondFailures % 100000 == 0) { |
88 warn("context %d: %d consecutive " |
89 "store conditional failures\n", |
90 xc->contextId(), stCondFailures); |
91 } 92 93 // store conditional failed already, so don't issue it to mem 94 return false; 95 } 96 } 97 98 return true; 99} 100 101} // namespace AlphaISA 102 103#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ |