1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#define __ARCH_ALPHA_LOCKED_MEM_HH__ 33 34/** 35 * @file 36 * 37 * ISA-specific helper functions for locked memory accesses. 38 */ 39 |
40#include "arch/alpha/miscregfile.hh" |
41#include "base/misc.hh" 42#include "mem/request.hh" 43 44 45namespace AlphaISA 46{ 47template <class XC> 48inline void 49handleLockedRead(XC *xc, Request *req) 50{ |
51 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 52 xc->setMiscReg(MISCREG_LOCKFLAG, true); |
53} 54 55 56template <class XC> 57inline bool 58handleLockedWrite(XC *xc, Request *req) 59{ 60 if (req->isUncacheable()) { 61 // Funky Turbolaser mailbox access...don't update 62 // result register (see stq_c in decoder.isa) 63 req->setScResult(2); 64 } else { 65 // standard store conditional |
66 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 67 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); |
68 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 69 // Lock flag not set or addr mismatch in CPU; 70 // don't even bother sending to memory system 71 req->setScResult(0); |
72 xc->setMiscReg(MISCREG_LOCKFLAG, false); |
73 // the rest of this code is not architectural; 74 // it's just a debugging aid to help detect 75 // livelock by warning on long sequences of failed 76 // store conditionals 77 int stCondFailures = xc->readStCondFailures(); 78 stCondFailures++; 79 xc->setStCondFailures(stCondFailures); 80 if (stCondFailures % 100000 == 0) { --- 17 unchanged lines hidden --- |