1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
32#define __ARCH_ALPHA_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 *
39 * Note that these functions are not embedded in the ISA description
40 * because they operate on the *physical* address rather than the
41 * virtual address. In the current M5 design, the physical address is
42 * not accessible from the ISA description, only from the CPU model.
43 * Thus the CPU is responsible for calling back to the ISA (here)
44 * after the address translation has been performed to allow the ISA
45 * to do these manipulations based on the physical address.
46 */
47
48#include "arch/alpha/miscregfile.hh"
49#include "base/misc.hh"
50#include "mem/request.hh"
51
52
53namespace AlphaISA
54{
55template <class XC>
56inline void
57handleLockedRead(XC *xc, Request *req)
58{
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
32#define __ARCH_ALPHA_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 *
39 * Note that these functions are not embedded in the ISA description
40 * because they operate on the *physical* address rather than the
41 * virtual address. In the current M5 design, the physical address is
42 * not accessible from the ISA description, only from the CPU model.
43 * Thus the CPU is responsible for calling back to the ISA (here)
44 * after the address translation has been performed to allow the ISA
45 * to do these manipulations based on the physical address.
46 */
47
48#include "arch/alpha/miscregfile.hh"
49#include "base/misc.hh"
50#include "mem/request.hh"
51
52
53namespace AlphaISA
54{
55template <class XC>
56inline void
57handleLockedRead(XC *xc, Request *req)
58{
|
59 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
60 xc->setMiscReg(MISCREG_LOCKFLAG, true);
| 59 xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
60 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true);
|
61}
62
63
64template <class XC>
65inline bool
66handleLockedWrite(XC *xc, Request *req)
67{
68 if (req->isUncacheable()) {
69 // Funky Turbolaser mailbox access...don't update
70 // result register (see stq_c in decoder.isa)
71 req->setExtraData(2);
72 } else {
73 // standard store conditional
| 61}
62
63
64template <class XC>
65inline bool
66handleLockedWrite(XC *xc, Request *req)
67{
68 if (req->isUncacheable()) {
69 // Funky Turbolaser mailbox access...don't update
70 // result register (see stq_c in decoder.isa)
71 req->setExtraData(2);
72 } else {
73 // standard store conditional
|
74 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
75 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
| 74 bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG);
75 Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR);
|
76 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
77 // Lock flag not set or addr mismatch in CPU;
78 // don't even bother sending to memory system
79 req->setExtraData(0);
| 76 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
77 // Lock flag not set or addr mismatch in CPU;
78 // don't even bother sending to memory system
79 req->setExtraData(0);
|
80 xc->setMiscReg(MISCREG_LOCKFLAG, false);
| 80 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false);
|
81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);
88 if (stCondFailures % 100000 == 0) {
89 warn("cpu %d: %d consecutive "
90 "store conditional failures\n",
91 xc->readCpuId(), stCondFailures);
92 }
93
94 // store conditional failed already, so don't issue it to mem
95 return false;
96 }
97 }
98
99 return true;
100}
101
102
103} // namespace AlphaISA
104
105#endif
| 81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);
88 if (stCondFailures % 100000 == 0) {
89 warn("cpu %d: %d consecutive "
90 "store conditional failures\n",
91 xc->readCpuId(), stCondFailures);
92 }
93
94 // store conditional failed already, so don't issue it to mem
95 return false;
96 }
97 }
98
99 return true;
100}
101
102
103} // namespace AlphaISA
104
105#endif
|