locked_mem.hh (7783:9b880b40ac10) | locked_mem.hh (9383:55fa95053ee8) |
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1/* | 1/* |
2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 42 * not accessible from the ISA description, only from the CPU model. 43 * Thus the CPU is responsible for calling back to the ISA (here) 44 * after the address translation has been performed to allow the ISA 45 * to do these manipulations based on the physical address. 46 */ 47 48#include "arch/alpha/registers.hh" 49#include "base/misc.hh" | 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 54 * not accessible from the ISA description, only from the CPU model. 55 * Thus the CPU is responsible for calling back to the ISA (here) 56 * after the address translation has been performed to allow the ISA 57 * to do these manipulations based on the physical address. 58 */ 59 60#include "arch/alpha/registers.hh" 61#include "base/misc.hh" |
62#include "mem/packet.hh" |
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50#include "mem/request.hh" 51 52namespace AlphaISA { 53 54template <class XC> 55inline void | 63#include "mem/request.hh" 64 65namespace AlphaISA { 66 67template <class XC> 68inline void |
69handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 70{ 71 // If we see a snoop come into the CPU and we currently have an LLSC 72 // operation pending we need to clear the lock flag if it is to the same 73 // cache line. 74 75 if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 76 return; 77 78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 79 Addr snoop_addr = pkt->getAddr(); 80 81 assert((cacheBlockMask & snoop_addr) == snoop_addr); 82 83 if (locked_addr == snoop_addr) 84 xc->setMiscReg(MISCREG_LOCKFLAG, false); 85} 86 87 88template <class XC> 89inline void |
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56handleLockedRead(XC *xc, Request *req) 57{ 58 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 59 xc->setMiscReg(MISCREG_LOCKFLAG, true); 60} 61 62 63template <class XC> --- 40 unchanged lines hidden --- | 90handleLockedRead(XC *xc, Request *req) 91{ 92 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 93 xc->setMiscReg(MISCREG_LOCKFLAG, true); 94} 95 96 97template <class XC> --- 40 unchanged lines hidden --- |