isa_traits.hh (6216:2f4020838149) isa_traits.hh (6227:a17798f2a52c)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 113 unchanged lines hidden (view full) ---

122 mode_executive = 1, // executive (unused by unix)
123 mode_supervisor = 2, // supervisor (unused by unix)
124 mode_user = 3, // user mode
125 mode_number // number of modes
126};
127
128// Constants Related to the number of registers
129
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 113 unchanged lines hidden (view full) ---

122 mode_executive = 1, // executive (unused by unix)
123 mode_supervisor = 2, // supervisor (unused by unix)
124 mode_user = 3, // user mode
125 mode_number // number of modes
126};
127
128// Constants Related to the number of registers
129
130const int NumIntArchRegs = 32;
131const int NumPALShadowRegs = 8;
132const int NumFloatArchRegs = 32;
133// @todo: Figure out what this number really should be.
134const int NumMiscArchRegs = 77;
130enum {
131 NumIntArchRegs = 32,
132 NumPALShadowRegs = 8,
133 NumFloatArchRegs = 32,
134 // @todo: Figure out what this number really should be.
135 NumMiscArchRegs = 77,
135
136
136const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
137const int NumFloatRegs = NumFloatArchRegs;
138const int NumMiscRegs = NumMiscArchRegs;
137 NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
138 NumFloatRegs = NumFloatArchRegs,
139 NumMiscRegs = NumMiscArchRegs,
139
140
140const int TotalNumRegs =
141 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
141 TotalNumRegs =
142 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs,
142
143
143const int TotalDataRegs = NumIntRegs + NumFloatRegs;
144 TotalDataRegs = NumIntRegs + NumFloatRegs,
144
145
145// semantically meaningful register indices
146const int ZeroReg = 31; // architecturally meaningful
147// the rest of these depend on the ABI
148const int StackPointerReg = 30;
149const int GlobalPointerReg = 29;
150const int ProcedureValueReg = 27;
151const int ReturnAddressReg = 26;
152const int ReturnValueReg = 0;
153const int FramePointerReg = 15;
146 // semantically meaningful register indices
147 ZeroReg = 31, // architecturally meaningful
148 // the rest of these depend on the ABI
149 StackPointerReg = 30,
150 GlobalPointerReg = 29,
151 ProcedureValueReg = 27,
152 ReturnAddressReg = 26,
153 ReturnValueReg = 0,
154 FramePointerReg = 15,
154
155
155const int SyscallNumReg = 0;
156const int FirstArgumentReg = 16;
157const int SyscallPseudoReturnReg = 20;
158const int SyscallSuccessReg = 19;
156 SyscallNumReg = 0,
157 FirstArgumentReg = 16,
158 SyscallPseudoReturnReg = 20,
159 SyscallSuccessReg = 19,
159
160
160const int LogVMPageSize = 13; // 8K bytes
161const int VMPageSize = (1 << LogVMPageSize);
161 LogVMPageSize = 13, // 8K bytes
162 VMPageSize = (1 << LogVMPageSize),
162
163
163const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
164 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
164
165
165const int MachineBytes = 8;
166const int WordBytes = 4;
167const int HalfwordBytes = 2;
168const int ByteBytes = 1;
166 MachineBytes = 8,
167 WordBytes = 4,
168 HalfwordBytes = 2,
169 ByteBytes = 1,
170};
169
170// return a no-op instruction... used for instruction fetch faults
171// Alpha UNOP (ldq_u r31,0(r0))
172const ExtMachInst NoopMachInst = 0x2ffe0000;
173
174} // namespace AlphaISA
175
176#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
171
172// return a no-op instruction... used for instruction fetch faults
173// Alpha UNOP (ldq_u r31,0(r0))
174const ExtMachInst NoopMachInst = 0x2ffe0000;
175
176} // namespace AlphaISA
177
178#endif // __ARCH_ALPHA_ISA_TRAITS_HH__