isa_traits.hh (5543:3af77710f397) | isa_traits.hh (5569:baeee670d4ce) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/alpha/ipr.hh" 38#include "arch/alpha/max_inst_regs.hh" 39#include "arch/alpha/types.hh" 40#include "config/full_system.hh" 41#include "sim/host.hh" 42 43class StaticInstPtr; 44 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/alpha/ipr.hh" 38#include "arch/alpha/max_inst_regs.hh" 39#include "arch/alpha/types.hh" 40#include "config/full_system.hh" 41#include "sim/host.hh" 42 43class StaticInstPtr; 44 |
45namespace AlphaISA 46{ 47 using namespace LittleEndianGuest; 48 using AlphaISAInst::MaxInstSrcRegs; 49 using AlphaISAInst::MaxInstDestRegs; | 45namespace AlphaISA { |
50 | 46 |
51 // These enumerate all the registers for dependence tracking. 52 enum DependenceTags { 53 // 0..31 are the integer regs 0..31 54 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 55 FP_Base_DepTag = 40, 56 Ctrl_Base_DepTag = 72 57 }; | 47using namespace LittleEndianGuest; 48using AlphaISAInst::MaxInstSrcRegs; 49using AlphaISAInst::MaxInstDestRegs; |
58 | 50 |
59 StaticInstPtr decodeInst(ExtMachInst); | 51// These enumerate all the registers for dependence tracking. 52enum DependenceTags { 53 // 0..31 are the integer regs 0..31 54 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 55 FP_Base_DepTag = 40, 56 Ctrl_Base_DepTag = 72 57}; |
60 | 58 |
61 // Alpha Does NOT have a delay slot 62 #define ISA_HAS_DELAY_SLOT 0 | 59StaticInstPtr decodeInst(ExtMachInst); |
63 | 60 |
64 const Addr PageShift = 13; 65 const Addr PageBytes = ULL(1) << PageShift; 66 const Addr PageMask = ~(PageBytes - 1); 67 const Addr PageOffset = PageBytes - 1; | 61// Alpha Does NOT have a delay slot 62#define ISA_HAS_DELAY_SLOT 0 |
68 | 63 |
64const Addr PageShift = 13; 65const Addr PageBytes = ULL(1) << PageShift; 66const Addr PageMask = ~(PageBytes - 1); 67const Addr PageOffset = PageBytes - 1; |
|
69 | 68 |
70 //////////////////////////////////////////////////////////////////////// 71 // 72 // Translation stuff 73 // | 69//////////////////////////////////////////////////////////////////////// 70// 71// Translation stuff 72// |
74 | 73 |
75 const Addr PteShift = 3; 76 const Addr NPtePageShift = PageShift - PteShift; 77 const Addr NPtePage = ULL(1) << NPtePageShift; 78 const Addr PteMask = NPtePage - 1; | 74const Addr PteShift = 3; 75const Addr NPtePageShift = PageShift - PteShift; 76const Addr NPtePage = ULL(1) << NPtePageShift; 77const Addr PteMask = NPtePage - 1; |
79 | 78 |
80 // User Virtual 81 const Addr USegBase = ULL(0x0); 82 const Addr USegEnd = ULL(0x000003ffffffffff); | 79// User Virtual 80const Addr USegBase = ULL(0x0); 81const Addr USegEnd = ULL(0x000003ffffffffff); |
83 | 82 |
84 // Kernel Direct Mapped 85 const Addr K0SegBase = ULL(0xfffffc0000000000); 86 const Addr K0SegEnd = ULL(0xfffffdffffffffff); | 83// Kernel Direct Mapped 84const Addr K0SegBase = ULL(0xfffffc0000000000); 85const Addr K0SegEnd = ULL(0xfffffdffffffffff); |
87 | 86 |
88 // Kernel Virtual 89 const Addr K1SegBase = ULL(0xfffffe0000000000); 90 const Addr K1SegEnd = ULL(0xffffffffffffffff); | 87// Kernel Virtual 88const Addr K1SegBase = ULL(0xfffffe0000000000); 89const Addr K1SegEnd = ULL(0xffffffffffffffff); |
91 | 90 |
92 // For loading... XXX This maybe could be USegEnd?? --ali 93 const Addr LoadAddrMask = ULL(0xffffffffff); | 91// For loading... XXX This maybe could be USegEnd?? --ali 92const Addr LoadAddrMask = ULL(0xffffffffff); |
94 | 93 |
95#if FULL_SYSTEM | 94//////////////////////////////////////////////////////////////////////// 95// 96// Interrupt levels 97// 98enum InterruptLevels 99{ 100 INTLEVEL_SOFTWARE_MIN = 4, 101 INTLEVEL_SOFTWARE_MAX = 19, |
96 | 102 |
97 //////////////////////////////////////////////////////////////////////// 98 // 99 // Interrupt levels 100 // 101 enum InterruptLevels 102 { 103 INTLEVEL_SOFTWARE_MIN = 4, 104 INTLEVEL_SOFTWARE_MAX = 19, | 103 INTLEVEL_EXTERNAL_MIN = 20, 104 INTLEVEL_EXTERNAL_MAX = 34, |
105 | 105 |
106 INTLEVEL_EXTERNAL_MIN = 20, 107 INTLEVEL_EXTERNAL_MAX = 34, | 106 INTLEVEL_IRQ0 = 20, 107 INTLEVEL_IRQ1 = 21, 108 INTINDEX_ETHERNET = 0, 109 INTINDEX_SCSI = 1, 110 INTLEVEL_IRQ2 = 22, 111 INTLEVEL_IRQ3 = 23, |
108 | 112 |
109 INTLEVEL_IRQ0 = 20, 110 INTLEVEL_IRQ1 = 21, 111 INTINDEX_ETHERNET = 0, 112 INTINDEX_SCSI = 1, 113 INTLEVEL_IRQ2 = 22, 114 INTLEVEL_IRQ3 = 23, | 113 INTLEVEL_SERIAL = 33, |
115 | 114 |
116 INTLEVEL_SERIAL = 33, | 115 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 116}; |
117 | 117 |
118 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 119 }; | 118// EV5 modes 119enum mode_type 120{ 121 mode_kernel = 0, // kernel 122 mode_executive = 1, // executive (unused by unix) 123 mode_supervisor = 2, // supervisor (unused by unix) 124 mode_user = 3, // user mode 125 mode_number // number of modes 126}; |
120 | 127 |
121#endif | 128// Constants Related to the number of registers |
122 | 129 |
123 // EV5 modes 124 enum mode_type 125 { 126 mode_kernel = 0, // kernel 127 mode_executive = 1, // executive (unused by unix) 128 mode_supervisor = 2, // supervisor (unused by unix) 129 mode_user = 3, // user mode 130 mode_number // number of modes 131 }; | 130const int NumIntArchRegs = 32; 131const int NumPALShadowRegs = 8; 132const int NumFloatArchRegs = 32; 133// @todo: Figure out what this number really should be. 134const int NumMiscArchRegs = 77; |
132 | 135 |
133 // Constants Related to the number of registers | 136const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 137const int NumFloatRegs = NumFloatArchRegs; 138const int NumMiscRegs = NumMiscArchRegs; |
134 | 139 |
135 const int NumIntArchRegs = 32; 136 const int NumPALShadowRegs = 8; 137 const int NumFloatArchRegs = 32; 138 // @todo: Figure out what this number really should be. 139 const int NumMiscArchRegs = 77; | 140const int TotalNumRegs = 141 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; |
140 | 142 |
141 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 142 const int NumFloatRegs = NumFloatArchRegs; 143 const int NumMiscRegs = NumMiscArchRegs; | 143const int TotalDataRegs = NumIntRegs + NumFloatRegs; |
144 | 144 |
145 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 146 NumMiscRegs + NumInternalProcRegs; | 145// semantically meaningful register indices 146const int ZeroReg = 31; // architecturally meaningful 147// the rest of these depend on the ABI 148const int StackPointerReg = 30; 149const int GlobalPointerReg = 29; 150const int ProcedureValueReg = 27; 151const int ReturnAddressReg = 26; 152const int ReturnValueReg = 0; 153const int FramePointerReg = 15; |
147 | 154 |
148 const int TotalDataRegs = NumIntRegs + NumFloatRegs; | 155const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 156const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); |
149 | 157 |
150 // semantically meaningful register indices 151 const int ZeroReg = 31; // architecturally meaningful 152 // the rest of these depend on the ABI 153 const int StackPointerReg = 30; 154 const int GlobalPointerReg = 29; 155 const int ProcedureValueReg = 27; 156 const int ReturnAddressReg = 26; 157 const int ReturnValueReg = 0; 158 const int FramePointerReg = 15; | 158const int SyscallNumReg = ReturnValueReg; 159const int SyscallPseudoReturnReg = ArgumentReg[4]; 160const int SyscallSuccessReg = 19; |
159 | 161 |
160 const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 161 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); | 162const int LogVMPageSize = 13; // 8K bytes 163const int VMPageSize = (1 << LogVMPageSize); |
162 | 164 |
163 const int SyscallNumReg = ReturnValueReg; 164 const int SyscallPseudoReturnReg = ArgumentReg[4]; 165 const int SyscallSuccessReg = 19; | 165const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned |
166 | 166 |
167 const int LogVMPageSize = 13; // 8K bytes 168 const int VMPageSize = (1 << LogVMPageSize); | 167const int MachineBytes = 8; 168const int WordBytes = 4; 169const int HalfwordBytes = 2; 170const int ByteBytes = 1; |
169 | 171 |
170 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned | 172// return a no-op instruction... used for instruction fetch faults 173// Alpha UNOP (ldq_u r31,0(r0)) 174const ExtMachInst NoopMachInst = 0x2ffe0000; |
171 | 175 |
172 const int MachineBytes = 8; 173 const int WordBytes = 4; 174 const int HalfwordBytes = 2; 175 const int ByteBytes = 1; | 176} // namespace AlphaISA |
176 | 177 |
177 // return a no-op instruction... used for instruction fetch faults 178 // Alpha UNOP (ldq_u r31,0(r0)) 179 const ExtMachInst NoopMachInst = 0x2ffe0000; 180 181}; 182 | |
183#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ | 178#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ |