isa_traits.hh (5228:b08c9c42907a) | isa_traits.hh (5543:3af77710f397) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 109 unchanged lines hidden (view full) --- 118 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 119 }; 120 121#endif 122 123 // EV5 modes 124 enum mode_type 125 { | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 109 unchanged lines hidden (view full) --- 118 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 119 }; 120 121#endif 122 123 // EV5 modes 124 enum mode_type 125 { |
126 mode_kernel = 0, // kernel 127 mode_executive = 1, // executive (unused by unix) 128 mode_supervisor = 2, // supervisor (unused by unix) 129 mode_user = 3, // user mode 130 mode_number // number of modes | 126 mode_kernel = 0, // kernel 127 mode_executive = 1, // executive (unused by unix) 128 mode_supervisor = 2, // supervisor (unused by unix) 129 mode_user = 3, // user mode 130 mode_number // number of modes |
131 }; 132 133 // Constants Related to the number of registers 134 135 const int NumIntArchRegs = 32; 136 const int NumPALShadowRegs = 8; 137 const int NumFloatArchRegs = 32; 138 // @todo: Figure out what this number really should be. --- 4 unchanged lines hidden (view full) --- 143 const int NumMiscRegs = NumMiscArchRegs; 144 145 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 146 NumMiscRegs + NumInternalProcRegs; 147 148 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 149 150 // semantically meaningful register indices | 131 }; 132 133 // Constants Related to the number of registers 134 135 const int NumIntArchRegs = 32; 136 const int NumPALShadowRegs = 8; 137 const int NumFloatArchRegs = 32; 138 // @todo: Figure out what this number really should be. --- 4 unchanged lines hidden (view full) --- 143 const int NumMiscRegs = NumMiscArchRegs; 144 145 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 146 NumMiscRegs + NumInternalProcRegs; 147 148 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 149 150 // semantically meaningful register indices |
151 const int ZeroReg = 31; // architecturally meaningful | 151 const int ZeroReg = 31; // architecturally meaningful |
152 // the rest of these depend on the ABI 153 const int StackPointerReg = 30; 154 const int GlobalPointerReg = 29; 155 const int ProcedureValueReg = 27; 156 const int ReturnAddressReg = 26; 157 const int ReturnValueReg = 0; 158 const int FramePointerReg = 15; 159 160 const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 161 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 162 163 const int SyscallNumReg = ReturnValueReg; 164 const int SyscallPseudoReturnReg = ArgumentReg[4]; 165 const int SyscallSuccessReg = 19; 166 | 152 // the rest of these depend on the ABI 153 const int StackPointerReg = 30; 154 const int GlobalPointerReg = 29; 155 const int ProcedureValueReg = 27; 156 const int ReturnAddressReg = 26; 157 const int ReturnValueReg = 0; 158 const int FramePointerReg = 15; 159 160 const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 161 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 162 163 const int SyscallNumReg = ReturnValueReg; 164 const int SyscallPseudoReturnReg = ArgumentReg[4]; 165 const int SyscallSuccessReg = 19; 166 |
167 const int LogVMPageSize = 13; // 8K bytes | 167 const int LogVMPageSize = 13; // 8K bytes |
168 const int VMPageSize = (1 << LogVMPageSize); 169 170 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 171 172 const int MachineBytes = 8; 173 const int WordBytes = 4; 174 const int HalfwordBytes = 2; 175 const int ByteBytes = 1; 176 177 // return a no-op instruction... used for instruction fetch faults 178 // Alpha UNOP (ldq_u r31,0(r0)) 179 const ExtMachInst NoopMachInst = 0x2ffe0000; 180 181}; 182 183#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ | 168 const int VMPageSize = (1 << LogVMPageSize); 169 170 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 171 172 const int MachineBytes = 8; 173 const int WordBytes = 4; 174 const int HalfwordBytes = 2; 175 const int ByteBytes = 1; 176 177 // return a no-op instruction... used for instruction fetch faults 178 // Alpha UNOP (ldq_u r31,0(r0)) 179 const ExtMachInst NoopMachInst = 0x2ffe0000; 180 181}; 182 183#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ |