1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 37#include "arch/alpha/types.hh" 38#include "config/full_system.hh" 39#include "sim/host.hh" 40 41class StaticInstPtr; 42 43namespace AlphaISA 44{
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45 using namespace LittleEndianGuest; |
46
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46 typedef uint32_t MachInst;
47 typedef uint64_t ExtMachInst;
48 typedef uint8_t RegIndex;
49
50 const int NumIntArchRegs = 32;
51 const int NumPALShadowRegs = 8;
52 const int NumFloatArchRegs = 32;
53 // @todo: Figure out what this number really should be.
54 const int NumMiscArchRegs = 32;
55
56 // Static instruction parameters
57 const int MaxInstSrcRegs = 3;
58 const int MaxInstDestRegs = 2;
59
60 // semantically meaningful register indices
61 const int ZeroReg = 31; // architecturally meaningful
62 // the rest of these depend on the ABI
63 const int StackPointerReg = 30;
64 const int GlobalPointerReg = 29;
65 const int ProcedureValueReg = 27;
66 const int ReturnAddressReg = 26;
67 const int ReturnValueReg = 0;
68 const int FramePointerReg = 15;
69 const int ArgumentReg0 = 16;
70 const int ArgumentReg1 = 17;
71 const int ArgumentReg2 = 18;
72 const int ArgumentReg3 = 19;
73 const int ArgumentReg4 = 20;
74 const int ArgumentReg5 = 21;
75 const int SyscallNumReg = ReturnValueReg;
76 const int SyscallPseudoReturnReg = ArgumentReg4;
77 const int SyscallSuccessReg = 19;
78
79
80
81 const int LogVMPageSize = 13; // 8K bytes
82 const int VMPageSize = (1 << LogVMPageSize);
83
84 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
85
86 const int WordBytes = 4;
87 const int HalfwordBytes = 2;
88 const int ByteBytes = 1;
89
90
91 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
92 const int NumFloatRegs = NumFloatArchRegs;
93 const int NumMiscRegs = NumMiscArchRegs;
94
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47 // These enumerate all the registers for dependence tracking. 48 enum DependenceTags { 49 // 0..31 are the integer regs 0..31 50 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 51 FP_Base_DepTag = 40, 52 Ctrl_Base_DepTag = 72, 53 Fpcr_DepTag = 72, // floating point control register 54 Uniq_DepTag = 73, 55 Lock_Flag_DepTag = 74, 56 Lock_Addr_DepTag = 75, 57 IPR_Base_DepTag = 76 58 }; 59
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108 typedef uint64_t IntReg;
109 typedef IntReg IntRegFile[NumIntRegs];
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60 StaticInstPtr decodeInst(ExtMachInst); |
61
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111 // floating point register file entry type
112 typedef union {
113 uint64_t q;
114 double d;
115 } FloatReg;
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62 // Alpha Does NOT have a delay slot 63 #define ISA_HAS_DELAY_SLOT 0 |
64
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117 typedef union {
118 uint64_t q[NumFloatRegs]; // integer qword view
119 double d[NumFloatRegs]; // double-precision floating point view
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65 const Addr PageShift = 13; 66 const Addr PageBytes = ULL(1) << PageShift; 67 const Addr PageMask = ~(PageBytes - 1); 68 const Addr PageOffset = PageBytes - 1; |
69
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121 void clear()
122 { bzero(d, sizeof(d)); }
123 } FloatRegFile;
124
125extern const Addr PageShift;
126extern const Addr PageBytes;
127extern const Addr PageMask;
128extern const Addr PageOffset;
129
130// redirected register map, really only used for the full system case.
131extern const int reg_redir[NumIntRegs];
132
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70#if FULL_SYSTEM 71
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135 typedef uint64_t InternalProcReg;
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72 //////////////////////////////////////////////////////////////////////// 73 // 74 // Translation stuff 75 // |
76
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137#include "arch/alpha/isa_fullsys_traits.hh"
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77 const Addr PteShift = 3; 78 const Addr NPtePageShift = PageShift - PteShift; 79 const Addr NPtePage = ULL(1) << NPtePageShift; 80 const Addr PteMask = NPtePage - 1; |
81
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139#else
140 const int NumInternalProcRegs = 0;
141#endif
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82 // User Virtual 83 const Addr USegBase = ULL(0x0); 84 const Addr USegEnd = ULL(0x000003ffffffffff); |
85
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143 // control register file contents
144 typedef uint64_t MiscReg;
145 class MiscRegFile {
146 protected:
147 uint64_t fpcr; // floating point condition codes
148 uint64_t uniq; // process-unique register
149 bool lock_flag; // lock flag for LL/SC
150 Addr lock_addr; // lock address for LL/SC
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86 // Kernel Direct Mapped 87 const Addr K0SegBase = ULL(0xfffffc0000000000); 88 const Addr K0SegEnd = ULL(0xfffffdffffffffff); |
89
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152 public:
153 MiscReg readReg(int misc_reg);
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90 // Kernel Virtual 91 const Addr K1SegBase = ULL(0xfffffe0000000000); 92 const Addr K1SegEnd = ULL(0xffffffffffffffff); |
93
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155 //These functions should be removed once the simplescalar cpu model
156 //has been replaced.
157 int getInstAsid();
158 int getDataAsid();
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94 // For loading... XXX This maybe could be USegEnd?? --ali 95 const Addr LoadAddrMask = ULL(0xffffffffff); |
96
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160 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
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97 //////////////////////////////////////////////////////////////////////// 98 // 99 // Interrupt levels 100 // 101 enum InterruptLevels 102 { 103 INTLEVEL_SOFTWARE_MIN = 4, 104 INTLEVEL_SOFTWARE_MAX = 19, |
105
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162 Fault setReg(int misc_reg, const MiscReg &val);
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106 INTLEVEL_EXTERNAL_MIN = 20, 107 INTLEVEL_EXTERNAL_MAX = 34, |
108
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164 Fault setRegWithEffect(int misc_reg, const MiscReg &val,
165 ExecContext *xc);
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109 INTLEVEL_IRQ0 = 20, 110 INTLEVEL_IRQ1 = 21, 111 INTINDEX_ETHERNET = 0, 112 INTINDEX_SCSI = 1, 113 INTLEVEL_IRQ2 = 22, 114 INTLEVEL_IRQ3 = 23, |
115
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167 void serialize(std::ostream &os);
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116 INTLEVEL_SERIAL = 33, |
117
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169 void unserialize(Checkpoint *cp, const std::string §ion);
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118 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 119 }; |
120
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171 void clear()
172 {
173 fpcr = uniq = 0;
174 lock_flag = 0;
175 lock_addr = 0;
176 }
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121
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178#if FULL_SYSTEM
179 protected:
180 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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122 // EV5 modes 123 enum mode_type 124 { 125 mode_kernel = 0, // kernel 126 mode_executive = 1, // executive (unused by unix) 127 mode_supervisor = 2, // supervisor (unused by unix) 128 mode_user = 3, // user mode 129 mode_number // number of modes 130 }; |
131
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182 private:
183 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
184
185 Fault setIpr(int idx, uint64_t val, ExecContext *xc);
186
187 void copyIprs(ExecContext *xc);
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132#endif
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189 friend class RegFile;
190 };
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133
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192 const int TotalNumRegs = NumIntRegs + NumFloatRegs +
193 NumMiscRegs + NumInternalProcRegs;
194
195 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
196
197 typedef union {
198 IntReg intreg;
199 FloatReg fpreg;
200 MiscReg ctrlreg;
201 } AnyReg;
202
203 struct RegFile {
204 IntRegFile intRegFile; // (signed) integer register file
205 FloatRegFile floatRegFile; // floating point register file
206 MiscRegFile miscRegs; // control register file
207 Addr pc; // program counter
208 Addr npc; // next-cycle program counter
209 Addr nnpc;
210
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134#if FULL_SYSTEM
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212 int intrflag; // interrupt flag
213 inline int instAsid()
214 { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
215 inline int dataAsid()
216 { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
217#endif // FULL_SYSTEM
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135 //////////////////////////////////////////////////////////////////////// 136 // 137 // Internal Processor Reigsters 138 // 139 enum md_ipr_names 140 { 141 IPR_ISR = 0x100, // interrupt summary register 142 IPR_ITB_TAG = 0x101, // ITLB tag register 143 IPR_ITB_PTE = 0x102, // ITLB page table entry register 144 IPR_ITB_ASN = 0x103, // ITLB address space register 145 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register 146 IPR_ITB_IA = 0x105, // ITLB invalidate all register 147 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register 148 IPR_ITB_IS = 0x107, // ITLB invalidate select register 149 IPR_SIRR = 0x108, // software interrupt request register 150 IPR_ASTRR = 0x109, // asynchronous system trap request register 151 IPR_ASTER = 0x10a, // asynchronous system trap enable register 152 IPR_EXC_ADDR = 0x10b, // exception address register 153 IPR_EXC_SUM = 0x10c, // exception summary register 154 IPR_EXC_MASK = 0x10d, // exception mask register 155 IPR_PAL_BASE = 0x10e, // PAL base address register 156 IPR_ICM = 0x10f, // instruction current mode 157 IPR_IPLR = 0x110, // interrupt priority level register 158 IPR_INTID = 0x111, // interrupt ID register 159 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register 160 IPR_IVPTBR = 0x113, // virtual page table base register 161 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register 162 IPR_SL_XMIT = 0x116, // serial line transmit register 163 IPR_SL_RCV = 0x117, // serial line receive register 164 IPR_ICSR = 0x118, // instruction control and status register 165 IPR_IC_FLUSH = 0x119, // instruction cache flush control 166 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register 167 IPR_PMCTR = 0x11c, // performance counter register |
168
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219 void serialize(std::ostream &os);
220 void unserialize(Checkpoint *cp, const std::string §ion);
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169 // PAL temporary registers... 170 // register meanings gleaned from osfpal.s source code 171 IPR_PALtemp0 = 0x140, // local scratch 172 IPR_PALtemp1 = 0x141, // local scratch 173 IPR_PALtemp2 = 0x142, // entUna 174 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer 175 IPR_PALtemp4 = 0x144, // memory management temp 176 IPR_PALtemp5 = 0x145, // memory management temp 177 IPR_PALtemp6 = 0x146, // memory management temp 178 IPR_PALtemp7 = 0x147, // entIF 179 IPR_PALtemp8 = 0x148, // intmask 180 IPR_PALtemp9 = 0x149, // entSys 181 IPR_PALtemp10 = 0x14a, // ?? 182 IPR_PALtemp11 = 0x14b, // entInt 183 IPR_PALtemp12 = 0x14c, // entArith 184 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL 185 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL 186 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL 187 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> 188 IPR_PALtemp17 = 0x151, // sysval 189 IPR_PALtemp18 = 0x152, // usp 190 IPR_PALtemp19 = 0x153, // ksp 191 IPR_PALtemp20 = 0x154, // PTBR 192 IPR_PALtemp21 = 0x155, // entMM 193 IPR_PALtemp22 = 0x156, // kgp 194 IPR_PALtemp23 = 0x157, // PCBB |
195
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222 void clear()
223 {
224 bzero(intRegFile, sizeof(intRegFile));
225 floatRegFile.clear();
226 miscRegs.clear();
227 }
228 };
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196 IPR_DTB_ASN = 0x200, // DTLB address space number register 197 IPR_DTB_CM = 0x201, // DTLB current mode register 198 IPR_DTB_TAG = 0x202, // DTLB tag register 199 IPR_DTB_PTE = 0x203, // DTLB page table entry register 200 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register |
201
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230 static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
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202 IPR_MM_STAT = 0x205, // data MMU fault status register 203 IPR_VA = 0x206, // fault virtual address register 204 IPR_VA_FORM = 0x207, // formatted virtual address register 205 IPR_MVPTBR = 0x208, // MTU virtual page table base register 206 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register 207 IPR_DTB_IA = 0x20a, // DTLB invalidate all register 208 IPR_DTB_IS = 0x20b, // DTLB invalidate single register 209 IPR_ALT_MODE = 0x20c, // alternate mode register 210 IPR_CC = 0x20d, // cycle counter register 211 IPR_CC_CTL = 0x20e, // cycle counter control register 212 IPR_MCSR = 0x20f, // MTU control register |
213
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232 StaticInstPtr decodeInst(ExtMachInst);
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214 IPR_DC_FLUSH = 0x210, 215 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register 216 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register 217 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register 218 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register 219 IPR_DC_MODE = 0x216, // Dcache mode register 220 IPR_MAF_MODE = 0x217, // miss address file mode register |
221
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234 // Alpha Does NOT have a delay slot
235 #define ISA_HAS_DELAY_SLOT 0
236
237 // return a no-op instruction... used for instruction fetch faults
238 extern const ExtMachInst NoopMachInst;
239
240 enum annotes {
241 ANNOTE_NONE = 0,
242 // An impossible number for instruction annotations
243 ITOUCH_ANNOTE = 0xffffffff,
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222 NumInternalProcRegs // number of IPR registers |
223 };
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224#else 225 const int NumInternalProcRegs = 0; 226#endif |
227
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246 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
247 panic("register classification not implemented");
248 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
249 }
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228 // Constants Related to the number of registers |
229
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251 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
252 panic("register classification not implemented");
253 return (reg >= 9 && reg <= 15);
254 }
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230 const int NumIntArchRegs = 32; 231 const int NumPALShadowRegs = 8; 232 const int NumFloatArchRegs = 32; 233 // @todo: Figure out what this number really should be. 234 const int NumMiscArchRegs = 32; |
235
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256 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
257 panic("register classification not implemented");
258 return false;
259 }
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236 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 237 const int NumFloatRegs = NumFloatArchRegs; 238 const int NumMiscRegs = NumMiscArchRegs; |
239
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261 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
262 panic("register classification not implemented");
263 return false;
264 }
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240 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 241 NumMiscRegs + NumInternalProcRegs; |
242
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266 static inline Addr alignAddress(const Addr &addr,
267 unsigned int nbytes) {
268 return (addr & ~(nbytes - 1));
269 }
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243 const int TotalDataRegs = NumIntRegs + NumFloatRegs; |
244
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271 // Instruction address compression hooks
272 static inline Addr realPCToFetchPC(const Addr &addr) {
273 return addr;
274 }
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245 // Static instruction parameters 246 const int MaxInstSrcRegs = 3; 247 const int MaxInstDestRegs = 2; |
248
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276 static inline Addr fetchPCToRealPC(const Addr &addr) {
277 return addr;
278 }
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249 // semantically meaningful register indices 250 const int ZeroReg = 31; // architecturally meaningful 251 // the rest of these depend on the ABI 252 const int StackPointerReg = 30; 253 const int GlobalPointerReg = 29; 254 const int ProcedureValueReg = 27; 255 const int ReturnAddressReg = 26; 256 const int ReturnValueReg = 0; 257 const int FramePointerReg = 15; 258 const int ArgumentReg0 = 16; 259 const int ArgumentReg1 = 17; 260 const int ArgumentReg2 = 18; 261 const int ArgumentReg3 = 19; 262 const int ArgumentReg4 = 20; 263 const int ArgumentReg5 = 21; 264 const int SyscallNumReg = ReturnValueReg; 265 const int SyscallPseudoReturnReg = ArgumentReg4; 266 const int SyscallSuccessReg = 19; |
267
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280 // the size of "fetched" instructions (not necessarily the size
281 // of real instructions for PISA)
282 static inline size_t fetchInstSize() {
283 return sizeof(MachInst);
284 }
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268 const int LogVMPageSize = 13; // 8K bytes 269 const int VMPageSize = (1 << LogVMPageSize); |
270
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286 static inline MachInst makeRegisterCopy(int dest, int src) {
287 panic("makeRegisterCopy not implemented");
288 return 0;
289 }
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271 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned |
272
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291 // Machine operations
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273 const int MachineBytes = 8; 274 const int WordBytes = 4; 275 const int HalfwordBytes = 2; 276 const int ByteBytes = 1; |
277
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293 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
294 int regnum);
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278 // return a no-op instruction... used for instruction fetch faults 279 // Alpha UNOP (ldq_u r31,0(r0)) 280 const ExtMachInst NoopMachInst = 0x2ffe0000; |
281
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296 void restoreMachineReg(RegFile ®s, const AnyReg ®,
297 int regnum);
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282 // redirected register map, really only used for the full system case. 283 extern const int reg_redir[NumIntRegs]; |
284
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299#if 0
300 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
301 const RegFile ®s);
302
303 static void unserializeSpecialRegs(const IniFile *db,
304 const std::string &category,
305 ConfigNode *node,
306 RegFile ®s);
307#endif
308
309 /**
310 * Function to insure ISA semantics about 0 registers.
311 * @param xc The execution context.
312 */
313 template <class XC>
314 void zeroRegisters(XC *xc);
315
316 const Addr MaxAddr = (Addr)-1;
317
318#if !FULL_SYSTEM
319 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
320 {
321 // check for error condition. Alpha syscall convention is to
322 // indicate success/failure in reg a3 (r19) and put the
323 // return value itself in the standard return value reg (v0).
324 if (return_value.successful()) {
325 // no error
326 regs->intRegFile[SyscallSuccessReg] = 0;
327 regs->intRegFile[ReturnValueReg] = return_value.value();
328 } else {
329 // got an error, return details
330 regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
331 regs->intRegFile[ReturnValueReg] = -return_value.value();
332 }
333 }
334#endif
335
336 void copyRegs(ExecContext *src, ExecContext *dest);
337
338 void copyMiscRegs(ExecContext *src, ExecContext *dest);
339
340#if FULL_SYSTEM
341 void copyIprs(ExecContext *src, ExecContext *dest);
342#endif
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285}; 286 287#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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