1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 |
37#include "arch/alpha/ipr.hh" |
38#include "arch/alpha/types.hh" 39#include "base/types.hh" 40#include "cpu/static_inst_fwd.hh" 41 42namespace AlphaISA { 43 44using namespace LittleEndianGuest; 45 --- 79 unchanged lines hidden (view full) --- 125 126// return a no-op instruction... used for instruction fetch faults 127// Alpha UNOP (ldq_u r31,0(r0)) 128const ExtMachInst NoopMachInst = 0x2ffe0000; 129 130// Memory accesses cannot be unaligned 131const bool HasUnalignedMemAcc = false; 132 |
133const bool CurThreadInfoImplemented = true; 134const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23; 135 |
136} // namespace AlphaISA 137 138#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ |