1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 142 unchanged lines hidden (view full) --- 151 const int ZeroReg = 31; // architecturally meaningful 152 // the rest of these depend on the ABI 153 const int StackPointerReg = 30; 154 const int GlobalPointerReg = 29; 155 const int ProcedureValueReg = 27; 156 const int ReturnAddressReg = 26; 157 const int ReturnValueReg = 0; 158 const int FramePointerReg = 15; |
159 160 const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 161 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 162 |
163 const int SyscallNumReg = ReturnValueReg; |
164 const int SyscallPseudoReturnReg = ArgumentReg[4]; |
165 const int SyscallSuccessReg = 19; 166 167 const int LogVMPageSize = 13; // 8K bytes 168 const int VMPageSize = (1 << LogVMPageSize); 169 170 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 171 172 const int MachineBytes = 8; 173 const int WordBytes = 4; 174 const int HalfwordBytes = 2; 175 const int ByteBytes = 1; 176 177 // return a no-op instruction... used for instruction fetch faults 178 // Alpha UNOP (ldq_u r31,0(r0)) 179 const ExtMachInst NoopMachInst = 0x2ffe0000; 180 181}; 182 183#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ |