1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/alpha/types.hh" 38#include "config/full_system.hh" 39#include "sim/host.hh" 40 41class StaticInstPtr; 42 43namespace AlphaISA 44{ |
45 |
46 typedef uint32_t MachInst; 47 typedef uint64_t ExtMachInst; 48 typedef uint8_t RegIndex; 49 50 const int NumIntArchRegs = 32; 51 const int NumPALShadowRegs = 8; 52 const int NumFloatArchRegs = 32; 53 // @todo: Figure out what this number really should be. 54 const int NumMiscArchRegs = 32; 55 56 // Static instruction parameters 57 const int MaxInstSrcRegs = 3; 58 const int MaxInstDestRegs = 2; 59 60 // semantically meaningful register indices 61 const int ZeroReg = 31; // architecturally meaningful 62 // the rest of these depend on the ABI 63 const int StackPointerReg = 30; 64 const int GlobalPointerReg = 29; 65 const int ProcedureValueReg = 27; 66 const int ReturnAddressReg = 26; 67 const int ReturnValueReg = 0; 68 const int FramePointerReg = 15; 69 const int ArgumentReg0 = 16; 70 const int ArgumentReg1 = 17; 71 const int ArgumentReg2 = 18; 72 const int ArgumentReg3 = 19; 73 const int ArgumentReg4 = 20; 74 const int ArgumentReg5 = 21; 75 const int SyscallNumReg = ReturnValueReg; 76 const int SyscallPseudoReturnReg = ArgumentReg4; 77 const int SyscallSuccessReg = 19; 78 79 80 81 const int LogVMPageSize = 13; // 8K bytes 82 const int VMPageSize = (1 << LogVMPageSize); 83 84 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 85 86 const int WordBytes = 4; 87 const int HalfwordBytes = 2; 88 const int ByteBytes = 1; 89 90 91 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 92 const int NumFloatRegs = NumFloatArchRegs; 93 const int NumMiscRegs = NumMiscArchRegs; 94 |
95 // These enumerate all the registers for dependence tracking. 96 enum DependenceTags { 97 // 0..31 are the integer regs 0..31 98 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 99 FP_Base_DepTag = 40, 100 Ctrl_Base_DepTag = 72, 101 Fpcr_DepTag = 72, // floating point control register 102 Uniq_DepTag = 73, 103 Lock_Flag_DepTag = 74, 104 Lock_Addr_DepTag = 75, 105 IPR_Base_DepTag = 76 106 }; 107 |
108 typedef uint64_t IntReg; 109 typedef IntReg IntRegFile[NumIntRegs]; |
110 |
111 // floating point register file entry type 112 typedef union { 113 uint64_t q; 114 double d; 115 } FloatReg; |
116 |
117 typedef union { 118 uint64_t q[NumFloatRegs]; // integer qword view 119 double d[NumFloatRegs]; // double-precision floating point view |
120 |
121 void clear() 122 { bzero(d, sizeof(d)); } 123 } FloatRegFile; 124 125extern const Addr PageShift; 126extern const Addr PageBytes; 127extern const Addr PageMask; 128extern const Addr PageOffset; 129 130// redirected register map, really only used for the full system case. 131extern const int reg_redir[NumIntRegs]; 132 |
133#if FULL_SYSTEM 134 |
135 typedef uint64_t InternalProcReg; |
136 |
137#include "arch/alpha/isa_fullsys_traits.hh" |
138 |
139#else 140 const int NumInternalProcRegs = 0; 141#endif |
142 |
143 // control register file contents 144 typedef uint64_t MiscReg; 145 class MiscRegFile { 146 protected: 147 uint64_t fpcr; // floating point condition codes 148 uint64_t uniq; // process-unique register 149 bool lock_flag; // lock flag for LL/SC 150 Addr lock_addr; // lock address for LL/SC |
151 |
152 public: 153 MiscReg readReg(int misc_reg); |
154 |
155 //These functions should be removed once the simplescalar cpu model 156 //has been replaced. 157 int getInstAsid(); 158 int getDataAsid(); |
159 |
160 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); |
161 |
162 Fault setReg(int misc_reg, const MiscReg &val); |
163 |
164 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 165 ExecContext *xc); |
166 |
167 void serialize(std::ostream &os); |
168 |
169 void unserialize(Checkpoint *cp, const std::string §ion); |
170 |
171 void clear() 172 { 173 fpcr = uniq = 0; 174 lock_flag = 0; 175 lock_addr = 0; 176 } |
177 |
178#if FULL_SYSTEM 179 protected: 180 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs |
181 |
182 private: 183 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); 184 185 Fault setIpr(int idx, uint64_t val, ExecContext *xc); 186 187 void copyIprs(ExecContext *xc); |
188#endif |
189 friend class RegFile; 190 }; |
191 |
192 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 193 NumMiscRegs + NumInternalProcRegs; 194 195 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 196 197 typedef union { 198 IntReg intreg; 199 FloatReg fpreg; 200 MiscReg ctrlreg; 201 } AnyReg; 202 203 struct RegFile { 204 IntRegFile intRegFile; // (signed) integer register file 205 FloatRegFile floatRegFile; // floating point register file 206 MiscRegFile miscRegs; // control register file 207 Addr pc; // program counter 208 Addr npc; // next-cycle program counter 209 Addr nnpc; 210 |
211#if FULL_SYSTEM |
212 int intrflag; // interrupt flag 213 inline int instAsid() 214 { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); } 215 inline int dataAsid() 216 { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); } 217#endif // FULL_SYSTEM |
218 |
219 void serialize(std::ostream &os); 220 void unserialize(Checkpoint *cp, const std::string §ion); |
221 |
222 void clear() 223 { 224 bzero(intRegFile, sizeof(intRegFile)); 225 floatRegFile.clear(); 226 miscRegs.clear(); 227 } 228 }; |
229 |
230 static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); |
231 |
232 StaticInstPtr decodeInst(ExtMachInst); |
233 |
234 // Alpha Does NOT have a delay slot 235 #define ISA_HAS_DELAY_SLOT 0 236 237 // return a no-op instruction... used for instruction fetch faults 238 extern const ExtMachInst NoopMachInst; 239 240 enum annotes { 241 ANNOTE_NONE = 0, 242 // An impossible number for instruction annotations 243 ITOUCH_ANNOTE = 0xffffffff, |
244 }; |
245 |
246 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 247 panic("register classification not implemented"); 248 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 249 } |
250 |
251 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 252 panic("register classification not implemented"); 253 return (reg >= 9 && reg <= 15); 254 } |
255 |
256 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 257 panic("register classification not implemented"); 258 return false; 259 } |
260 |
261 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 262 panic("register classification not implemented"); 263 return false; 264 } |
265 |
266 static inline Addr alignAddress(const Addr &addr, 267 unsigned int nbytes) { 268 return (addr & ~(nbytes - 1)); 269 } |
270 |
271 // Instruction address compression hooks 272 static inline Addr realPCToFetchPC(const Addr &addr) { 273 return addr; 274 } |
275 |
276 static inline Addr fetchPCToRealPC(const Addr &addr) { 277 return addr; 278 } |
279 |
280 // the size of "fetched" instructions (not necessarily the size 281 // of real instructions for PISA) 282 static inline size_t fetchInstSize() { 283 return sizeof(MachInst); 284 } |
285 |
286 static inline MachInst makeRegisterCopy(int dest, int src) { 287 panic("makeRegisterCopy not implemented"); 288 return 0; 289 } |
290 |
291 // Machine operations |
292 |
293 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 294 int regnum); |
295 |
296 void restoreMachineReg(RegFile ®s, const AnyReg ®, 297 int regnum); |
298 |
299#if 0 300 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 301 const RegFile ®s); 302 303 static void unserializeSpecialRegs(const IniFile *db, 304 const std::string &category, 305 ConfigNode *node, 306 RegFile ®s); 307#endif 308 309 /** 310 * Function to insure ISA semantics about 0 registers. 311 * @param xc The execution context. 312 */ 313 template <class XC> 314 void zeroRegisters(XC *xc); 315 316 const Addr MaxAddr = (Addr)-1; 317 318#if !FULL_SYSTEM 319 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 320 { 321 // check for error condition. Alpha syscall convention is to 322 // indicate success/failure in reg a3 (r19) and put the 323 // return value itself in the standard return value reg (v0). 324 if (return_value.successful()) { 325 // no error 326 regs->intRegFile[SyscallSuccessReg] = 0; 327 regs->intRegFile[ReturnValueReg] = return_value.value(); 328 } else { 329 // got an error, return details 330 regs->intRegFile[SyscallSuccessReg] = (IntReg) -1; 331 regs->intRegFile[ReturnValueReg] = -return_value.value(); 332 } 333 } 334#endif 335 336 void copyRegs(ExecContext *src, ExecContext *dest); 337 338 void copyMiscRegs(ExecContext *src, ExecContext *dest); 339 340#if FULL_SYSTEM 341 void copyIprs(ExecContext *src, ExecContext *dest); 342#endif |
343}; 344 345#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ |