45,49c45
< namespace AlphaISA
< {
< using namespace LittleEndianGuest;
< using AlphaISAInst::MaxInstSrcRegs;
< using AlphaISAInst::MaxInstDestRegs;
---
> namespace AlphaISA {
51,57c47,49
< // These enumerate all the registers for dependence tracking.
< enum DependenceTags {
< // 0..31 are the integer regs 0..31
< // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
< FP_Base_DepTag = 40,
< Ctrl_Base_DepTag = 72
< };
---
> using namespace LittleEndianGuest;
> using AlphaISAInst::MaxInstSrcRegs;
> using AlphaISAInst::MaxInstDestRegs;
59c51,57
< StaticInstPtr decodeInst(ExtMachInst);
---
> // These enumerate all the registers for dependence tracking.
> enum DependenceTags {
> // 0..31 are the integer regs 0..31
> // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
> FP_Base_DepTag = 40,
> Ctrl_Base_DepTag = 72
> };
61,62c59
< // Alpha Does NOT have a delay slot
< #define ISA_HAS_DELAY_SLOT 0
---
> StaticInstPtr decodeInst(ExtMachInst);
64,67c61,62
< const Addr PageShift = 13;
< const Addr PageBytes = ULL(1) << PageShift;
< const Addr PageMask = ~(PageBytes - 1);
< const Addr PageOffset = PageBytes - 1;
---
> // Alpha Does NOT have a delay slot
> #define ISA_HAS_DELAY_SLOT 0
68a64,67
> const Addr PageShift = 13;
> const Addr PageBytes = ULL(1) << PageShift;
> const Addr PageMask = ~(PageBytes - 1);
> const Addr PageOffset = PageBytes - 1;
70,73c69,72
< ////////////////////////////////////////////////////////////////////////
< //
< // Translation stuff
< //
---
> ////////////////////////////////////////////////////////////////////////
> //
> // Translation stuff
> //
75,78c74,77
< const Addr PteShift = 3;
< const Addr NPtePageShift = PageShift - PteShift;
< const Addr NPtePage = ULL(1) << NPtePageShift;
< const Addr PteMask = NPtePage - 1;
---
> const Addr PteShift = 3;
> const Addr NPtePageShift = PageShift - PteShift;
> const Addr NPtePage = ULL(1) << NPtePageShift;
> const Addr PteMask = NPtePage - 1;
80,82c79,81
< // User Virtual
< const Addr USegBase = ULL(0x0);
< const Addr USegEnd = ULL(0x000003ffffffffff);
---
> // User Virtual
> const Addr USegBase = ULL(0x0);
> const Addr USegEnd = ULL(0x000003ffffffffff);
84,86c83,85
< // Kernel Direct Mapped
< const Addr K0SegBase = ULL(0xfffffc0000000000);
< const Addr K0SegEnd = ULL(0xfffffdffffffffff);
---
> // Kernel Direct Mapped
> const Addr K0SegBase = ULL(0xfffffc0000000000);
> const Addr K0SegEnd = ULL(0xfffffdffffffffff);
88,90c87,89
< // Kernel Virtual
< const Addr K1SegBase = ULL(0xfffffe0000000000);
< const Addr K1SegEnd = ULL(0xffffffffffffffff);
---
> // Kernel Virtual
> const Addr K1SegBase = ULL(0xfffffe0000000000);
> const Addr K1SegEnd = ULL(0xffffffffffffffff);
92,93c91,92
< // For loading... XXX This maybe could be USegEnd?? --ali
< const Addr LoadAddrMask = ULL(0xffffffffff);
---
> // For loading... XXX This maybe could be USegEnd?? --ali
> const Addr LoadAddrMask = ULL(0xffffffffff);
95c94,101
< #if FULL_SYSTEM
---
> ////////////////////////////////////////////////////////////////////////
> //
> // Interrupt levels
> //
> enum InterruptLevels
> {
> INTLEVEL_SOFTWARE_MIN = 4,
> INTLEVEL_SOFTWARE_MAX = 19,
97,104c103,104
< ////////////////////////////////////////////////////////////////////////
< //
< // Interrupt levels
< //
< enum InterruptLevels
< {
< INTLEVEL_SOFTWARE_MIN = 4,
< INTLEVEL_SOFTWARE_MAX = 19,
---
> INTLEVEL_EXTERNAL_MIN = 20,
> INTLEVEL_EXTERNAL_MAX = 34,
106,107c106,111
< INTLEVEL_EXTERNAL_MIN = 20,
< INTLEVEL_EXTERNAL_MAX = 34,
---
> INTLEVEL_IRQ0 = 20,
> INTLEVEL_IRQ1 = 21,
> INTINDEX_ETHERNET = 0,
> INTINDEX_SCSI = 1,
> INTLEVEL_IRQ2 = 22,
> INTLEVEL_IRQ3 = 23,
109,114c113
< INTLEVEL_IRQ0 = 20,
< INTLEVEL_IRQ1 = 21,
< INTINDEX_ETHERNET = 0,
< INTINDEX_SCSI = 1,
< INTLEVEL_IRQ2 = 22,
< INTLEVEL_IRQ3 = 23,
---
> INTLEVEL_SERIAL = 33,
116c115,116
< INTLEVEL_SERIAL = 33,
---
> NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
> };
118,119c118,126
< NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
< };
---
> // EV5 modes
> enum mode_type
> {
> mode_kernel = 0, // kernel
> mode_executive = 1, // executive (unused by unix)
> mode_supervisor = 2, // supervisor (unused by unix)
> mode_user = 3, // user mode
> mode_number // number of modes
> };
121c128
< #endif
---
> // Constants Related to the number of registers
123,131c130,134
< // EV5 modes
< enum mode_type
< {
< mode_kernel = 0, // kernel
< mode_executive = 1, // executive (unused by unix)
< mode_supervisor = 2, // supervisor (unused by unix)
< mode_user = 3, // user mode
< mode_number // number of modes
< };
---
> const int NumIntArchRegs = 32;
> const int NumPALShadowRegs = 8;
> const int NumFloatArchRegs = 32;
> // @todo: Figure out what this number really should be.
> const int NumMiscArchRegs = 77;
133c136,138
< // Constants Related to the number of registers
---
> const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
> const int NumFloatRegs = NumFloatArchRegs;
> const int NumMiscRegs = NumMiscArchRegs;
135,139c140,141
< const int NumIntArchRegs = 32;
< const int NumPALShadowRegs = 8;
< const int NumFloatArchRegs = 32;
< // @todo: Figure out what this number really should be.
< const int NumMiscArchRegs = 77;
---
> const int TotalNumRegs =
> NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
141,143c143
< const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
< const int NumFloatRegs = NumFloatArchRegs;
< const int NumMiscRegs = NumMiscArchRegs;
---
> const int TotalDataRegs = NumIntRegs + NumFloatRegs;
145,146c145,153
< const int TotalNumRegs = NumIntRegs + NumFloatRegs +
< NumMiscRegs + NumInternalProcRegs;
---
> // semantically meaningful register indices
> const int ZeroReg = 31; // architecturally meaningful
> // the rest of these depend on the ABI
> const int StackPointerReg = 30;
> const int GlobalPointerReg = 29;
> const int ProcedureValueReg = 27;
> const int ReturnAddressReg = 26;
> const int ReturnValueReg = 0;
> const int FramePointerReg = 15;
148c155,156
< const int TotalDataRegs = NumIntRegs + NumFloatRegs;
---
> const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
> const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
150,158c158,160
< // semantically meaningful register indices
< const int ZeroReg = 31; // architecturally meaningful
< // the rest of these depend on the ABI
< const int StackPointerReg = 30;
< const int GlobalPointerReg = 29;
< const int ProcedureValueReg = 27;
< const int ReturnAddressReg = 26;
< const int ReturnValueReg = 0;
< const int FramePointerReg = 15;
---
> const int SyscallNumReg = ReturnValueReg;
> const int SyscallPseudoReturnReg = ArgumentReg[4];
> const int SyscallSuccessReg = 19;
160,161c162,163
< const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
< const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
---
> const int LogVMPageSize = 13; // 8K bytes
> const int VMPageSize = (1 << LogVMPageSize);
163,165c165
< const int SyscallNumReg = ReturnValueReg;
< const int SyscallPseudoReturnReg = ArgumentReg[4];
< const int SyscallSuccessReg = 19;
---
> const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
167,168c167,170
< const int LogVMPageSize = 13; // 8K bytes
< const int VMPageSize = (1 << LogVMPageSize);
---
> const int MachineBytes = 8;
> const int WordBytes = 4;
> const int HalfwordBytes = 2;
> const int ByteBytes = 1;
170c172,174
< const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
---
> // return a no-op instruction... used for instruction fetch faults
> // Alpha UNOP (ldq_u r31,0(r0))
> const ExtMachInst NoopMachInst = 0x2ffe0000;
172,175c176
< const int MachineBytes = 8;
< const int WordBytes = 4;
< const int HalfwordBytes = 2;
< const int ByteBytes = 1;
---
> } // namespace AlphaISA
177,182d177
< // return a no-op instruction... used for instruction fetch faults
< // Alpha UNOP (ldq_u r31,0(r0))
< const ExtMachInst NoopMachInst = 0x2ffe0000;
<
< };
<
< namespace AlphaISA
< {
< using namespace LittleEndianGuest;
< using AlphaISAInst::MaxInstSrcRegs;
< using AlphaISAInst::MaxInstDestRegs;
---
> namespace AlphaISA {
51,57c47,49
< // These enumerate all the registers for dependence tracking.
< enum DependenceTags {
< // 0..31 are the integer regs 0..31
< // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
< FP_Base_DepTag = 40,
< Ctrl_Base_DepTag = 72
< };
---
> using namespace LittleEndianGuest;
> using AlphaISAInst::MaxInstSrcRegs;
> using AlphaISAInst::MaxInstDestRegs;
59c51,57
< StaticInstPtr decodeInst(ExtMachInst);
---
> // These enumerate all the registers for dependence tracking.
> enum DependenceTags {
> // 0..31 are the integer regs 0..31
> // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
> FP_Base_DepTag = 40,
> Ctrl_Base_DepTag = 72
> };
61,62c59
< // Alpha Does NOT have a delay slot
< #define ISA_HAS_DELAY_SLOT 0
---
> StaticInstPtr decodeInst(ExtMachInst);
64,67c61,62
< const Addr PageShift = 13;
< const Addr PageBytes = ULL(1) << PageShift;
< const Addr PageMask = ~(PageBytes - 1);
< const Addr PageOffset = PageBytes - 1;
---
> // Alpha Does NOT have a delay slot
> #define ISA_HAS_DELAY_SLOT 0
68a64,67
> const Addr PageShift = 13;
> const Addr PageBytes = ULL(1) << PageShift;
> const Addr PageMask = ~(PageBytes - 1);
> const Addr PageOffset = PageBytes - 1;
70,73c69,72
< ////////////////////////////////////////////////////////////////////////
< //
< // Translation stuff
< //
---
> ////////////////////////////////////////////////////////////////////////
> //
> // Translation stuff
> //
75,78c74,77
< const Addr PteShift = 3;
< const Addr NPtePageShift = PageShift - PteShift;
< const Addr NPtePage = ULL(1) << NPtePageShift;
< const Addr PteMask = NPtePage - 1;
---
> const Addr PteShift = 3;
> const Addr NPtePageShift = PageShift - PteShift;
> const Addr NPtePage = ULL(1) << NPtePageShift;
> const Addr PteMask = NPtePage - 1;
80,82c79,81
< // User Virtual
< const Addr USegBase = ULL(0x0);
< const Addr USegEnd = ULL(0x000003ffffffffff);
---
> // User Virtual
> const Addr USegBase = ULL(0x0);
> const Addr USegEnd = ULL(0x000003ffffffffff);
84,86c83,85
< // Kernel Direct Mapped
< const Addr K0SegBase = ULL(0xfffffc0000000000);
< const Addr K0SegEnd = ULL(0xfffffdffffffffff);
---
> // Kernel Direct Mapped
> const Addr K0SegBase = ULL(0xfffffc0000000000);
> const Addr K0SegEnd = ULL(0xfffffdffffffffff);
88,90c87,89
< // Kernel Virtual
< const Addr K1SegBase = ULL(0xfffffe0000000000);
< const Addr K1SegEnd = ULL(0xffffffffffffffff);
---
> // Kernel Virtual
> const Addr K1SegBase = ULL(0xfffffe0000000000);
> const Addr K1SegEnd = ULL(0xffffffffffffffff);
92,93c91,92
< // For loading... XXX This maybe could be USegEnd?? --ali
< const Addr LoadAddrMask = ULL(0xffffffffff);
---
> // For loading... XXX This maybe could be USegEnd?? --ali
> const Addr LoadAddrMask = ULL(0xffffffffff);
95c94,101
< #if FULL_SYSTEM
---
> ////////////////////////////////////////////////////////////////////////
> //
> // Interrupt levels
> //
> enum InterruptLevels
> {
> INTLEVEL_SOFTWARE_MIN = 4,
> INTLEVEL_SOFTWARE_MAX = 19,
97,104c103,104
< ////////////////////////////////////////////////////////////////////////
< //
< // Interrupt levels
< //
< enum InterruptLevels
< {
< INTLEVEL_SOFTWARE_MIN = 4,
< INTLEVEL_SOFTWARE_MAX = 19,
---
> INTLEVEL_EXTERNAL_MIN = 20,
> INTLEVEL_EXTERNAL_MAX = 34,
106,107c106,111
< INTLEVEL_EXTERNAL_MIN = 20,
< INTLEVEL_EXTERNAL_MAX = 34,
---
> INTLEVEL_IRQ0 = 20,
> INTLEVEL_IRQ1 = 21,
> INTINDEX_ETHERNET = 0,
> INTINDEX_SCSI = 1,
> INTLEVEL_IRQ2 = 22,
> INTLEVEL_IRQ3 = 23,
109,114c113
< INTLEVEL_IRQ0 = 20,
< INTLEVEL_IRQ1 = 21,
< INTINDEX_ETHERNET = 0,
< INTINDEX_SCSI = 1,
< INTLEVEL_IRQ2 = 22,
< INTLEVEL_IRQ3 = 23,
---
> INTLEVEL_SERIAL = 33,
116c115,116
< INTLEVEL_SERIAL = 33,
---
> NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
> };
118,119c118,126
< NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
< };
---
> // EV5 modes
> enum mode_type
> {
> mode_kernel = 0, // kernel
> mode_executive = 1, // executive (unused by unix)
> mode_supervisor = 2, // supervisor (unused by unix)
> mode_user = 3, // user mode
> mode_number // number of modes
> };
121c128
< #endif
---
> // Constants Related to the number of registers
123,131c130,134
< // EV5 modes
< enum mode_type
< {
< mode_kernel = 0, // kernel
< mode_executive = 1, // executive (unused by unix)
< mode_supervisor = 2, // supervisor (unused by unix)
< mode_user = 3, // user mode
< mode_number // number of modes
< };
---
> const int NumIntArchRegs = 32;
> const int NumPALShadowRegs = 8;
> const int NumFloatArchRegs = 32;
> // @todo: Figure out what this number really should be.
> const int NumMiscArchRegs = 77;
133c136,138
< // Constants Related to the number of registers
---
> const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
> const int NumFloatRegs = NumFloatArchRegs;
> const int NumMiscRegs = NumMiscArchRegs;
135,139c140,141
< const int NumIntArchRegs = 32;
< const int NumPALShadowRegs = 8;
< const int NumFloatArchRegs = 32;
< // @todo: Figure out what this number really should be.
< const int NumMiscArchRegs = 77;
---
> const int TotalNumRegs =
> NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
141,143c143
< const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
< const int NumFloatRegs = NumFloatArchRegs;
< const int NumMiscRegs = NumMiscArchRegs;
---
> const int TotalDataRegs = NumIntRegs + NumFloatRegs;
145,146c145,153
< const int TotalNumRegs = NumIntRegs + NumFloatRegs +
< NumMiscRegs + NumInternalProcRegs;
---
> // semantically meaningful register indices
> const int ZeroReg = 31; // architecturally meaningful
> // the rest of these depend on the ABI
> const int StackPointerReg = 30;
> const int GlobalPointerReg = 29;
> const int ProcedureValueReg = 27;
> const int ReturnAddressReg = 26;
> const int ReturnValueReg = 0;
> const int FramePointerReg = 15;
148c155,156
< const int TotalDataRegs = NumIntRegs + NumFloatRegs;
---
> const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
> const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
150,158c158,160
< // semantically meaningful register indices
< const int ZeroReg = 31; // architecturally meaningful
< // the rest of these depend on the ABI
< const int StackPointerReg = 30;
< const int GlobalPointerReg = 29;
< const int ProcedureValueReg = 27;
< const int ReturnAddressReg = 26;
< const int ReturnValueReg = 0;
< const int FramePointerReg = 15;
---
> const int SyscallNumReg = ReturnValueReg;
> const int SyscallPseudoReturnReg = ArgumentReg[4];
> const int SyscallSuccessReg = 19;
160,161c162,163
< const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
< const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
---
> const int LogVMPageSize = 13; // 8K bytes
> const int VMPageSize = (1 << LogVMPageSize);
163,165c165
< const int SyscallNumReg = ReturnValueReg;
< const int SyscallPseudoReturnReg = ArgumentReg[4];
< const int SyscallSuccessReg = 19;
---
> const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
167,168c167,170
< const int LogVMPageSize = 13; // 8K bytes
< const int VMPageSize = (1 << LogVMPageSize);
---
> const int MachineBytes = 8;
> const int WordBytes = 4;
> const int HalfwordBytes = 2;
> const int ByteBytes = 1;
170c172,174
< const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
---
> // return a no-op instruction... used for instruction fetch faults
> // Alpha UNOP (ldq_u r31,0(r0))
> const ExtMachInst NoopMachInst = 0x2ffe0000;
172,175c176
< const int MachineBytes = 8;
< const int WordBytes = 4;
< const int HalfwordBytes = 2;
< const int ByteBytes = 1;
---
> } // namespace AlphaISA
177,182d177
< // return a no-op instruction... used for instruction fetch faults
< // Alpha UNOP (ldq_u r31,0(r0))
< const ExtMachInst NoopMachInst = 0x2ffe0000;
<
< };
<