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> #include "arch/alpha/ipr.hh"
135,228d135
< #if FULL_SYSTEM
< ////////////////////////////////////////////////////////////////////////
< //
< // Internal Processor Reigsters
< //
< enum md_ipr_names
< {
< IPR_ISR = 0x100, // interrupt summary register
< IPR_ITB_TAG = 0x101, // ITLB tag register
< IPR_ITB_PTE = 0x102, // ITLB page table entry register
< IPR_ITB_ASN = 0x103, // ITLB address space register
< IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
< IPR_ITB_IA = 0x105, // ITLB invalidate all register
< IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
< IPR_ITB_IS = 0x107, // ITLB invalidate select register
< IPR_SIRR = 0x108, // software interrupt request register
< IPR_ASTRR = 0x109, // asynchronous system trap request register
< IPR_ASTER = 0x10a, // asynchronous system trap enable register
< IPR_EXC_ADDR = 0x10b, // exception address register
< IPR_EXC_SUM = 0x10c, // exception summary register
< IPR_EXC_MASK = 0x10d, // exception mask register
< IPR_PAL_BASE = 0x10e, // PAL base address register
< IPR_ICM = 0x10f, // instruction current mode
< IPR_IPLR = 0x110, // interrupt priority level register
< IPR_INTID = 0x111, // interrupt ID register
< IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
< IPR_IVPTBR = 0x113, // virtual page table base register
< IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
< IPR_SL_XMIT = 0x116, // serial line transmit register
< IPR_SL_RCV = 0x117, // serial line receive register
< IPR_ICSR = 0x118, // instruction control and status register
< IPR_IC_FLUSH = 0x119, // instruction cache flush control
< IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
< IPR_PMCTR = 0x11c, // performance counter register
<
< // PAL temporary registers...
< // register meanings gleaned from osfpal.s source code
< IPR_PALtemp0 = 0x140, // local scratch
< IPR_PALtemp1 = 0x141, // local scratch
< IPR_PALtemp2 = 0x142, // entUna
< IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
< IPR_PALtemp4 = 0x144, // memory management temp
< IPR_PALtemp5 = 0x145, // memory management temp
< IPR_PALtemp6 = 0x146, // memory management temp
< IPR_PALtemp7 = 0x147, // entIF
< IPR_PALtemp8 = 0x148, // intmask
< IPR_PALtemp9 = 0x149, // entSys
< IPR_PALtemp10 = 0x14a, // ??
< IPR_PALtemp11 = 0x14b, // entInt
< IPR_PALtemp12 = 0x14c, // entArith
< IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
< IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
< IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
< IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
< IPR_PALtemp17 = 0x151, // sysval
< IPR_PALtemp18 = 0x152, // usp
< IPR_PALtemp19 = 0x153, // ksp
< IPR_PALtemp20 = 0x154, // PTBR
< IPR_PALtemp21 = 0x155, // entMM
< IPR_PALtemp22 = 0x156, // kgp
< IPR_PALtemp23 = 0x157, // PCBB
<
< IPR_DTB_ASN = 0x200, // DTLB address space number register
< IPR_DTB_CM = 0x201, // DTLB current mode register
< IPR_DTB_TAG = 0x202, // DTLB tag register
< IPR_DTB_PTE = 0x203, // DTLB page table entry register
< IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
<
< IPR_MM_STAT = 0x205, // data MMU fault status register
< IPR_VA = 0x206, // fault virtual address register
< IPR_VA_FORM = 0x207, // formatted virtual address register
< IPR_MVPTBR = 0x208, // MTU virtual page table base register
< IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
< IPR_DTB_IA = 0x20a, // DTLB invalidate all register
< IPR_DTB_IS = 0x20b, // DTLB invalidate single register
< IPR_ALT_MODE = 0x20c, // alternate mode register
< IPR_CC = 0x20d, // cycle counter register
< IPR_CC_CTL = 0x20e, // cycle counter control register
< IPR_MCSR = 0x20f, // MTU control register
<
< IPR_DC_FLUSH = 0x210,
< IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
< IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
< IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
< IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
< IPR_DC_MODE = 0x216, // Dcache mode register
< IPR_MAF_MODE = 0x217, // miss address file mode register
<
< NumInternalProcRegs // number of IPR registers
< };
< #else
< const int NumInternalProcRegs = 0;
< #endif
<
> #include "arch/alpha/ipr.hh"
135,228d135
< #if FULL_SYSTEM
< ////////////////////////////////////////////////////////////////////////
< //
< // Internal Processor Reigsters
< //
< enum md_ipr_names
< {
< IPR_ISR = 0x100, // interrupt summary register
< IPR_ITB_TAG = 0x101, // ITLB tag register
< IPR_ITB_PTE = 0x102, // ITLB page table entry register
< IPR_ITB_ASN = 0x103, // ITLB address space register
< IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
< IPR_ITB_IA = 0x105, // ITLB invalidate all register
< IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
< IPR_ITB_IS = 0x107, // ITLB invalidate select register
< IPR_SIRR = 0x108, // software interrupt request register
< IPR_ASTRR = 0x109, // asynchronous system trap request register
< IPR_ASTER = 0x10a, // asynchronous system trap enable register
< IPR_EXC_ADDR = 0x10b, // exception address register
< IPR_EXC_SUM = 0x10c, // exception summary register
< IPR_EXC_MASK = 0x10d, // exception mask register
< IPR_PAL_BASE = 0x10e, // PAL base address register
< IPR_ICM = 0x10f, // instruction current mode
< IPR_IPLR = 0x110, // interrupt priority level register
< IPR_INTID = 0x111, // interrupt ID register
< IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
< IPR_IVPTBR = 0x113, // virtual page table base register
< IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
< IPR_SL_XMIT = 0x116, // serial line transmit register
< IPR_SL_RCV = 0x117, // serial line receive register
< IPR_ICSR = 0x118, // instruction control and status register
< IPR_IC_FLUSH = 0x119, // instruction cache flush control
< IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
< IPR_PMCTR = 0x11c, // performance counter register
<
< // PAL temporary registers...
< // register meanings gleaned from osfpal.s source code
< IPR_PALtemp0 = 0x140, // local scratch
< IPR_PALtemp1 = 0x141, // local scratch
< IPR_PALtemp2 = 0x142, // entUna
< IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
< IPR_PALtemp4 = 0x144, // memory management temp
< IPR_PALtemp5 = 0x145, // memory management temp
< IPR_PALtemp6 = 0x146, // memory management temp
< IPR_PALtemp7 = 0x147, // entIF
< IPR_PALtemp8 = 0x148, // intmask
< IPR_PALtemp9 = 0x149, // entSys
< IPR_PALtemp10 = 0x14a, // ??
< IPR_PALtemp11 = 0x14b, // entInt
< IPR_PALtemp12 = 0x14c, // entArith
< IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
< IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
< IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
< IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
< IPR_PALtemp17 = 0x151, // sysval
< IPR_PALtemp18 = 0x152, // usp
< IPR_PALtemp19 = 0x153, // ksp
< IPR_PALtemp20 = 0x154, // PTBR
< IPR_PALtemp21 = 0x155, // entMM
< IPR_PALtemp22 = 0x156, // kgp
< IPR_PALtemp23 = 0x157, // PCBB
<
< IPR_DTB_ASN = 0x200, // DTLB address space number register
< IPR_DTB_CM = 0x201, // DTLB current mode register
< IPR_DTB_TAG = 0x202, // DTLB tag register
< IPR_DTB_PTE = 0x203, // DTLB page table entry register
< IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
<
< IPR_MM_STAT = 0x205, // data MMU fault status register
< IPR_VA = 0x206, // fault virtual address register
< IPR_VA_FORM = 0x207, // formatted virtual address register
< IPR_MVPTBR = 0x208, // MTU virtual page table base register
< IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
< IPR_DTB_IA = 0x20a, // DTLB invalidate all register
< IPR_DTB_IS = 0x20b, // DTLB invalidate single register
< IPR_ALT_MODE = 0x20c, // alternate mode register
< IPR_CC = 0x20d, // cycle counter register
< IPR_CC_CTL = 0x20e, // cycle counter control register
< IPR_MCSR = 0x20f, // MTU control register
<
< IPR_DC_FLUSH = 0x210,
< IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
< IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
< IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
< IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
< IPR_DC_MODE = 0x216, // Dcache mode register
< IPR_MAF_MODE = 0x217, // miss address file mode register
<
< NumInternalProcRegs // number of IPR registers
< };
< #else
< const int NumInternalProcRegs = 0;
< #endif
<