1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/types.hh"
38#include "config/full_system.hh"
39#include "sim/host.hh"
40
41class StaticInstPtr;
42
43namespace AlphaISA
44{
45
46 using namespace LittleEndianGuest;
47
48 // These enumerate all the registers for dependence tracking.
49 enum DependenceTags {
50 // 0..31 are the integer regs 0..31
51 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
52 FP_Base_DepTag = 40,
53 Ctrl_Base_DepTag = 72,
54 Fpcr_DepTag = 72, // floating point control register
55 Uniq_DepTag = 73,
56 Lock_Flag_DepTag = 74,
57 Lock_Addr_DepTag = 75,
58 IPR_Base_DepTag = 76
59 };
60
61 StaticInstPtr decodeInst(ExtMachInst);
62
63 const Addr PageShift = 13;
64 const Addr PageBytes = ULL(1) << PageShift;
65 const Addr PageMask = ~(PageBytes - 1);
66 const Addr PageOffset = PageBytes - 1;
67
68
69#if FULL_SYSTEM
70
71 ////////////////////////////////////////////////////////////////////////
72 //
73 // Translation stuff
74 //
75
76 const Addr PteShift = 3;
77 const Addr NPtePageShift = PageShift - PteShift;
78 const Addr NPtePage = ULL(1) << NPtePageShift;
79 const Addr PteMask = NPtePage - 1;
80
81 // User Virtual
82 const Addr USegBase = ULL(0x0);
83 const Addr USegEnd = ULL(0x000003ffffffffff);
84
85 // Kernel Direct Mapped
86 const Addr K0SegBase = ULL(0xfffffc0000000000);
87 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
88
89 // Kernel Virtual
90 const Addr K1SegBase = ULL(0xfffffe0000000000);
91 const Addr K1SegEnd = ULL(0xffffffffffffffff);
92
93 // For loading... XXX This maybe could be USegEnd?? --ali
94 const Addr LoadAddrMask = ULL(0xffffffffff);
95
96 ////////////////////////////////////////////////////////////////////////
97 //
98 // Interrupt levels
99 //
100 enum InterruptLevels
101 {
102 INTLEVEL_SOFTWARE_MIN = 4,
103 INTLEVEL_SOFTWARE_MAX = 19,
104
105 INTLEVEL_EXTERNAL_MIN = 20,
106 INTLEVEL_EXTERNAL_MAX = 34,
107
108 INTLEVEL_IRQ0 = 20,
109 INTLEVEL_IRQ1 = 21,
110 INTINDEX_ETHERNET = 0,
111 INTINDEX_SCSI = 1,
112 INTLEVEL_IRQ2 = 22,
113 INTLEVEL_IRQ3 = 23,
114
115 INTLEVEL_SERIAL = 33,
116
117 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
118 };
119
120
121 // EV5 modes
122 enum mode_type
123 {
124 mode_kernel = 0, // kernel
125 mode_executive = 1, // executive (unused by unix)
126 mode_supervisor = 2, // supervisor (unused by unix)
127 mode_user = 3, // user mode
128 mode_number // number of modes
129 };
130
131#endif
132
133#if FULL_SYSTEM
134 ////////////////////////////////////////////////////////////////////////
135 //
136 // Internal Processor Reigsters
137 //
138 enum md_ipr_names
139 {
140 IPR_ISR = 0x100, // interrupt summary register
141 IPR_ITB_TAG = 0x101, // ITLB tag register
142 IPR_ITB_PTE = 0x102, // ITLB page table entry register
143 IPR_ITB_ASN = 0x103, // ITLB address space register
144 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
145 IPR_ITB_IA = 0x105, // ITLB invalidate all register
146 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
147 IPR_ITB_IS = 0x107, // ITLB invalidate select register
148 IPR_SIRR = 0x108, // software interrupt request register
149 IPR_ASTRR = 0x109, // asynchronous system trap request register
150 IPR_ASTER = 0x10a, // asynchronous system trap enable register
151 IPR_EXC_ADDR = 0x10b, // exception address register
152 IPR_EXC_SUM = 0x10c, // exception summary register
153 IPR_EXC_MASK = 0x10d, // exception mask register
154 IPR_PAL_BASE = 0x10e, // PAL base address register
155 IPR_ICM = 0x10f, // instruction current mode
156 IPR_IPLR = 0x110, // interrupt priority level register
157 IPR_INTID = 0x111, // interrupt ID register
158 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
159 IPR_IVPTBR = 0x113, // virtual page table base register
160 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
161 IPR_SL_XMIT = 0x116, // serial line transmit register
162 IPR_SL_RCV = 0x117, // serial line receive register
163 IPR_ICSR = 0x118, // instruction control and status register
164 IPR_IC_FLUSH = 0x119, // instruction cache flush control
165 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
166 IPR_PMCTR = 0x11c, // performance counter register
167
168 // PAL temporary registers...
169 // register meanings gleaned from osfpal.s source code
170 IPR_PALtemp0 = 0x140, // local scratch
171 IPR_PALtemp1 = 0x141, // local scratch
172 IPR_PALtemp2 = 0x142, // entUna
173 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
174 IPR_PALtemp4 = 0x144, // memory management temp
175 IPR_PALtemp5 = 0x145, // memory management temp
176 IPR_PALtemp6 = 0x146, // memory management temp
177 IPR_PALtemp7 = 0x147, // entIF
178 IPR_PALtemp8 = 0x148, // intmask
179 IPR_PALtemp9 = 0x149, // entSys
180 IPR_PALtemp10 = 0x14a, // ??
181 IPR_PALtemp11 = 0x14b, // entInt
182 IPR_PALtemp12 = 0x14c, // entArith
183 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
184 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
185 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
186 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
187 IPR_PALtemp17 = 0x151, // sysval
188 IPR_PALtemp18 = 0x152, // usp
189 IPR_PALtemp19 = 0x153, // ksp
190 IPR_PALtemp20 = 0x154, // PTBR
191 IPR_PALtemp21 = 0x155, // entMM
192 IPR_PALtemp22 = 0x156, // kgp
193 IPR_PALtemp23 = 0x157, // PCBB
194
195 IPR_DTB_ASN = 0x200, // DTLB address space number register
196 IPR_DTB_CM = 0x201, // DTLB current mode register
197 IPR_DTB_TAG = 0x202, // DTLB tag register
198 IPR_DTB_PTE = 0x203, // DTLB page table entry register
199 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
200
201 IPR_MM_STAT = 0x205, // data MMU fault status register
202 IPR_VA = 0x206, // fault virtual address register
203 IPR_VA_FORM = 0x207, // formatted virtual address register
204 IPR_MVPTBR = 0x208, // MTU virtual page table base register
205 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
206 IPR_DTB_IA = 0x20a, // DTLB invalidate all register
207 IPR_DTB_IS = 0x20b, // DTLB invalidate single register
208 IPR_ALT_MODE = 0x20c, // alternate mode register
209 IPR_CC = 0x20d, // cycle counter register
210 IPR_CC_CTL = 0x20e, // cycle counter control register
211 IPR_MCSR = 0x20f, // MTU control register
212
213 IPR_DC_FLUSH = 0x210,
214 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
215 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
216 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
217 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
218 IPR_DC_MODE = 0x216, // Dcache mode register
219 IPR_MAF_MODE = 0x217, // miss address file mode register
220
221 NumInternalProcRegs // number of IPR registers
222 };
223#else
224 const int NumInternalProcRegs = 0;
225#endif
226
227 // Constants Related to the number of registers
228
229 const int NumIntArchRegs = 32;
230 const int NumPALShadowRegs = 8;
231 const int NumFloatArchRegs = 32;
232 // @todo: Figure out what this number really should be.
233 const int NumMiscArchRegs = 32;
234
235 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
236 const int NumFloatRegs = NumFloatArchRegs;
237 const int NumMiscRegs = NumMiscArchRegs;
238
239 const int TotalNumRegs = NumIntRegs + NumFloatRegs +
240 NumMiscRegs + NumInternalProcRegs;
241
242 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
243
244 // Static instruction parameters
245 const int MaxInstSrcRegs = 3;
246 const int MaxInstDestRegs = 2;
247
248 // semantically meaningful register indices
249 const int ZeroReg = 31; // architecturally meaningful
250 // the rest of these depend on the ABI
251 const int StackPointerReg = 30;
252 const int GlobalPointerReg = 29;
253 const int ProcedureValueReg = 27;
254 const int ReturnAddressReg = 26;
255 const int ReturnValueReg = 0;
256 const int FramePointerReg = 15;
257 const int ArgumentReg0 = 16;
258 const int ArgumentReg1 = 17;
259 const int ArgumentReg2 = 18;
260 const int ArgumentReg3 = 19;
261 const int ArgumentReg4 = 20;
262 const int ArgumentReg5 = 21;
263 const int SyscallNumReg = ReturnValueReg;
264 const int SyscallPseudoReturnReg = ArgumentReg4;
265 const int SyscallSuccessReg = 19;
266
267 const int LogVMPageSize = 13; // 8K bytes
268 const int VMPageSize = (1 << LogVMPageSize);
269
270 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
271
272 const int MachineBytes = 8;
273 const int WordBytes = 4;
274 const int HalfwordBytes = 2;
275 const int ByteBytes = 1;
276
277 // return a no-op instruction... used for instruction fetch faults
278 // Alpha UNOP (ldq_u r31,0(r0))
279 const ExtMachInst NoopMachInst = 0x2ffe0000;
280
281 // redirected register map, really only used for the full system case.
282 extern const int reg_redir[NumIntRegs];
283
284};
285
286#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/types.hh"
38#include "config/full_system.hh"
39#include "sim/host.hh"
40
41class StaticInstPtr;
42
43namespace AlphaISA
44{
45
46 using namespace LittleEndianGuest;
47
48 // These enumerate all the registers for dependence tracking.
49 enum DependenceTags {
50 // 0..31 are the integer regs 0..31
51 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
52 FP_Base_DepTag = 40,
53 Ctrl_Base_DepTag = 72,
54 Fpcr_DepTag = 72, // floating point control register
55 Uniq_DepTag = 73,
56 Lock_Flag_DepTag = 74,
57 Lock_Addr_DepTag = 75,
58 IPR_Base_DepTag = 76
59 };
60
61 StaticInstPtr decodeInst(ExtMachInst);
62
63 const Addr PageShift = 13;
64 const Addr PageBytes = ULL(1) << PageShift;
65 const Addr PageMask = ~(PageBytes - 1);
66 const Addr PageOffset = PageBytes - 1;
67
68
69#if FULL_SYSTEM
70
71 ////////////////////////////////////////////////////////////////////////
72 //
73 // Translation stuff
74 //
75
76 const Addr PteShift = 3;
77 const Addr NPtePageShift = PageShift - PteShift;
78 const Addr NPtePage = ULL(1) << NPtePageShift;
79 const Addr PteMask = NPtePage - 1;
80
81 // User Virtual
82 const Addr USegBase = ULL(0x0);
83 const Addr USegEnd = ULL(0x000003ffffffffff);
84
85 // Kernel Direct Mapped
86 const Addr K0SegBase = ULL(0xfffffc0000000000);
87 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
88
89 // Kernel Virtual
90 const Addr K1SegBase = ULL(0xfffffe0000000000);
91 const Addr K1SegEnd = ULL(0xffffffffffffffff);
92
93 // For loading... XXX This maybe could be USegEnd?? --ali
94 const Addr LoadAddrMask = ULL(0xffffffffff);
95
96 ////////////////////////////////////////////////////////////////////////
97 //
98 // Interrupt levels
99 //
100 enum InterruptLevels
101 {
102 INTLEVEL_SOFTWARE_MIN = 4,
103 INTLEVEL_SOFTWARE_MAX = 19,
104
105 INTLEVEL_EXTERNAL_MIN = 20,
106 INTLEVEL_EXTERNAL_MAX = 34,
107
108 INTLEVEL_IRQ0 = 20,
109 INTLEVEL_IRQ1 = 21,
110 INTINDEX_ETHERNET = 0,
111 INTINDEX_SCSI = 1,
112 INTLEVEL_IRQ2 = 22,
113 INTLEVEL_IRQ3 = 23,
114
115 INTLEVEL_SERIAL = 33,
116
117 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
118 };
119
120
121 // EV5 modes
122 enum mode_type
123 {
124 mode_kernel = 0, // kernel
125 mode_executive = 1, // executive (unused by unix)
126 mode_supervisor = 2, // supervisor (unused by unix)
127 mode_user = 3, // user mode
128 mode_number // number of modes
129 };
130
131#endif
132
133#if FULL_SYSTEM
134 ////////////////////////////////////////////////////////////////////////
135 //
136 // Internal Processor Reigsters
137 //
138 enum md_ipr_names
139 {
140 IPR_ISR = 0x100, // interrupt summary register
141 IPR_ITB_TAG = 0x101, // ITLB tag register
142 IPR_ITB_PTE = 0x102, // ITLB page table entry register
143 IPR_ITB_ASN = 0x103, // ITLB address space register
144 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
145 IPR_ITB_IA = 0x105, // ITLB invalidate all register
146 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
147 IPR_ITB_IS = 0x107, // ITLB invalidate select register
148 IPR_SIRR = 0x108, // software interrupt request register
149 IPR_ASTRR = 0x109, // asynchronous system trap request register
150 IPR_ASTER = 0x10a, // asynchronous system trap enable register
151 IPR_EXC_ADDR = 0x10b, // exception address register
152 IPR_EXC_SUM = 0x10c, // exception summary register
153 IPR_EXC_MASK = 0x10d, // exception mask register
154 IPR_PAL_BASE = 0x10e, // PAL base address register
155 IPR_ICM = 0x10f, // instruction current mode
156 IPR_IPLR = 0x110, // interrupt priority level register
157 IPR_INTID = 0x111, // interrupt ID register
158 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
159 IPR_IVPTBR = 0x113, // virtual page table base register
160 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
161 IPR_SL_XMIT = 0x116, // serial line transmit register
162 IPR_SL_RCV = 0x117, // serial line receive register
163 IPR_ICSR = 0x118, // instruction control and status register
164 IPR_IC_FLUSH = 0x119, // instruction cache flush control
165 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
166 IPR_PMCTR = 0x11c, // performance counter register
167
168 // PAL temporary registers...
169 // register meanings gleaned from osfpal.s source code
170 IPR_PALtemp0 = 0x140, // local scratch
171 IPR_PALtemp1 = 0x141, // local scratch
172 IPR_PALtemp2 = 0x142, // entUna
173 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
174 IPR_PALtemp4 = 0x144, // memory management temp
175 IPR_PALtemp5 = 0x145, // memory management temp
176 IPR_PALtemp6 = 0x146, // memory management temp
177 IPR_PALtemp7 = 0x147, // entIF
178 IPR_PALtemp8 = 0x148, // intmask
179 IPR_PALtemp9 = 0x149, // entSys
180 IPR_PALtemp10 = 0x14a, // ??
181 IPR_PALtemp11 = 0x14b, // entInt
182 IPR_PALtemp12 = 0x14c, // entArith
183 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
184 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
185 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
186 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
187 IPR_PALtemp17 = 0x151, // sysval
188 IPR_PALtemp18 = 0x152, // usp
189 IPR_PALtemp19 = 0x153, // ksp
190 IPR_PALtemp20 = 0x154, // PTBR
191 IPR_PALtemp21 = 0x155, // entMM
192 IPR_PALtemp22 = 0x156, // kgp
193 IPR_PALtemp23 = 0x157, // PCBB
194
195 IPR_DTB_ASN = 0x200, // DTLB address space number register
196 IPR_DTB_CM = 0x201, // DTLB current mode register
197 IPR_DTB_TAG = 0x202, // DTLB tag register
198 IPR_DTB_PTE = 0x203, // DTLB page table entry register
199 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
200
201 IPR_MM_STAT = 0x205, // data MMU fault status register
202 IPR_VA = 0x206, // fault virtual address register
203 IPR_VA_FORM = 0x207, // formatted virtual address register
204 IPR_MVPTBR = 0x208, // MTU virtual page table base register
205 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
206 IPR_DTB_IA = 0x20a, // DTLB invalidate all register
207 IPR_DTB_IS = 0x20b, // DTLB invalidate single register
208 IPR_ALT_MODE = 0x20c, // alternate mode register
209 IPR_CC = 0x20d, // cycle counter register
210 IPR_CC_CTL = 0x20e, // cycle counter control register
211 IPR_MCSR = 0x20f, // MTU control register
212
213 IPR_DC_FLUSH = 0x210,
214 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
215 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
216 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
217 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
218 IPR_DC_MODE = 0x216, // Dcache mode register
219 IPR_MAF_MODE = 0x217, // miss address file mode register
220
221 NumInternalProcRegs // number of IPR registers
222 };
223#else
224 const int NumInternalProcRegs = 0;
225#endif
226
227 // Constants Related to the number of registers
228
229 const int NumIntArchRegs = 32;
230 const int NumPALShadowRegs = 8;
231 const int NumFloatArchRegs = 32;
232 // @todo: Figure out what this number really should be.
233 const int NumMiscArchRegs = 32;
234
235 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
236 const int NumFloatRegs = NumFloatArchRegs;
237 const int NumMiscRegs = NumMiscArchRegs;
238
239 const int TotalNumRegs = NumIntRegs + NumFloatRegs +
240 NumMiscRegs + NumInternalProcRegs;
241
242 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
243
244 // Static instruction parameters
245 const int MaxInstSrcRegs = 3;
246 const int MaxInstDestRegs = 2;
247
248 // semantically meaningful register indices
249 const int ZeroReg = 31; // architecturally meaningful
250 // the rest of these depend on the ABI
251 const int StackPointerReg = 30;
252 const int GlobalPointerReg = 29;
253 const int ProcedureValueReg = 27;
254 const int ReturnAddressReg = 26;
255 const int ReturnValueReg = 0;
256 const int FramePointerReg = 15;
257 const int ArgumentReg0 = 16;
258 const int ArgumentReg1 = 17;
259 const int ArgumentReg2 = 18;
260 const int ArgumentReg3 = 19;
261 const int ArgumentReg4 = 20;
262 const int ArgumentReg5 = 21;
263 const int SyscallNumReg = ReturnValueReg;
264 const int SyscallPseudoReturnReg = ArgumentReg4;
265 const int SyscallSuccessReg = 19;
266
267 const int LogVMPageSize = 13; // 8K bytes
268 const int VMPageSize = (1 << LogVMPageSize);
269
270 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
271
272 const int MachineBytes = 8;
273 const int WordBytes = 4;
274 const int HalfwordBytes = 2;
275 const int ByteBytes = 1;
276
277 // return a no-op instruction... used for instruction fetch faults
278 // Alpha UNOP (ldq_u r31,0(r0))
279 const ExtMachInst NoopMachInst = 0x2ffe0000;
280
281 // redirected register map, really only used for the full system case.
282 extern const int reg_redir[NumIntRegs];
283
284};
285
286#endif // __ARCH_ALPHA_ISA_TRAITS_HH__