1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 149 unchanged lines hidden (view full) --- 158 %(class_name)s::%(class_name)s(ExtMachInst machInst) 159 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 160 { 161 %(constructor)s; 162 } 163}}; 164 165def template EACompExecute {{ |
166 Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, |
167 Trace::InstRecord *traceData) const 168 { 169 Addr EA; 170 Fault fault = NoFault; 171 172 %(fp_enable_check)s; 173 %(op_decl)s; 174 %(op_rd)s; --- 5 unchanged lines hidden (view full) --- 180 } 181 182 return fault; 183 } 184}}; 185 186 187def template LoadExecute {{ |
188 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, |
189 Trace::InstRecord *traceData) const 190 { 191 Addr EA; 192 Fault fault = NoFault; 193 194 %(fp_enable_check)s; 195 %(op_decl)s; 196 %(op_rd)s; --- 9 unchanged lines hidden (view full) --- 206 } 207 208 return fault; 209 } 210}}; 211 212 213def template LoadInitiateAcc {{ |
214 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, |
215 Trace::InstRecord *traceData) const 216 { 217 Addr EA; 218 Fault fault = NoFault; 219 220 %(fp_enable_check)s; 221 %(op_src_decl)s; 222 %(op_rd)s; --- 5 unchanged lines hidden (view full) --- 228 229 return fault; 230 } 231}}; 232 233 234def template LoadCompleteAcc {{ 235 Fault %(class_name)s::completeAcc(PacketPtr pkt, |
236 CPU_EXEC_CONTEXT *xc, |
237 Trace::InstRecord *traceData) const 238 { 239 Fault fault = NoFault; 240 241 %(fp_enable_check)s; 242 %(op_decl)s; 243 244 getMem(pkt, Mem, traceData); --- 7 unchanged lines hidden (view full) --- 252 } 253 254 return fault; 255 } 256}}; 257 258 259def template StoreExecute {{ |
260 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, |
261 Trace::InstRecord *traceData) const 262 { 263 Addr EA; 264 Fault fault = NoFault; 265 266 %(fp_enable_check)s; 267 %(op_decl)s; 268 %(op_rd)s; --- 16 unchanged lines hidden (view full) --- 285 %(op_wb)s; 286 } 287 288 return fault; 289 } 290}}; 291 292def template StoreCondExecute {{ |
293 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, |
294 Trace::InstRecord *traceData) const 295 { 296 Addr EA; 297 Fault fault = NoFault; 298 uint64_t write_result = 0; 299 300 %(fp_enable_check)s; 301 %(op_decl)s; --- 17 unchanged lines hidden (view full) --- 319 %(op_wb)s; 320 } 321 322 return fault; 323 } 324}}; 325 326def template StoreInitiateAcc {{ |
327 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, |
328 Trace::InstRecord *traceData) const 329 { 330 Addr EA; 331 Fault fault = NoFault; 332 333 %(fp_enable_check)s; 334 %(op_decl)s; 335 %(op_rd)s; --- 10 unchanged lines hidden (view full) --- 346 347 return fault; 348 } 349}}; 350 351 352def template StoreCompleteAcc {{ 353 Fault %(class_name)s::completeAcc(PacketPtr pkt, |
354 CPU_EXEC_CONTEXT *xc, |
355 Trace::InstRecord *traceData) const 356 { 357 return NoFault; 358 } 359}}; 360 361 362def template StoreCondCompleteAcc {{ 363 Fault %(class_name)s::completeAcc(PacketPtr pkt, |
364 CPU_EXEC_CONTEXT *xc, |
365 Trace::InstRecord *traceData) const 366 { 367 Fault fault = NoFault; 368 369 %(fp_enable_check)s; 370 %(op_dest_decl)s; 371 372 uint64_t write_result = pkt->req->getExtraData(); --- 7 unchanged lines hidden (view full) --- 380 } 381 382 return fault; 383 } 384}}; 385 386 387def template MiscExecute {{ |
388 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, |
389 Trace::InstRecord *traceData) const 390 { 391 Addr EA M5_VAR_USED; 392 Fault fault = NoFault; 393 394 %(fp_enable_check)s; 395 %(op_decl)s; 396 %(op_rd)s; --- 6 unchanged lines hidden (view full) --- 403 404 return NoFault; 405 } 406}}; 407 408// Prefetches in Alpha don't actually do anything 409// They just build an effective address and complete 410def template MiscInitiateAcc {{ |
411 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, |
412 Trace::InstRecord *traceData) const 413 { 414 warn("initiateAcc undefined: Misc instruction does not support split " 415 "access method!"); 416 return NoFault; 417 } 418}}; 419 420 421def template MiscCompleteAcc {{ 422 Fault %(class_name)s::completeAcc(PacketPtr pkt, |
423 CPU_EXEC_CONTEXT *xc, |
424 Trace::InstRecord *traceData) const 425 { 426 warn("completeAcc undefined: Misc instruction does not support split " 427 "access method!"); 428 429 return NoFault; 430 } 431}}; --- 129 unchanged lines hidden --- |