28
29////////////////////////////////////////////////////////////////////
30//
31// Memory-format instructions: LoadAddress, Load, Store
32//
33
34output header {{
35 /**
36 * Base class for general Alpha memory-format instructions.
37 */
38 class Memory : public AlphaStaticInst
39 {
40 protected:
41
42 /// Memory request flags. See mem_req_base.hh.
43 unsigned memAccessFlags;
44 /// Pointer to EAComp object.
45 const StaticInstPtr eaCompPtr;
46 /// Pointer to MemAcc object.
47 const StaticInstPtr memAccPtr;
48
49 /// Constructor
50 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
51 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
52 StaticInstPtr _memAccPtr = nullStaticInstPtr)
53 : AlphaStaticInst(mnem, _machInst, __opClass),
54 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
55 {
56 }
57
58 std::string
59 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
60
61 public:
62
63 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
64 const StaticInstPtr &memAccInst() const { return memAccPtr; }
65 };
66
67 /**
68 * Base class for memory-format instructions using a 32-bit
69 * displacement (i.e. most of them).
70 */
71 class MemoryDisp32 : public Memory
72 {
73 protected:
74 /// Displacement for EA calculation (signed).
75 int32_t disp;
76
77 /// Constructor.
78 MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
79 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
80 StaticInstPtr _memAccPtr = nullStaticInstPtr)
81 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
82 disp(MEMDISP)
83 {
84 }
85 };
86
87
88 /**
89 * Base class for a few miscellaneous memory-format insts
90 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
91 * None of these instructions has a destination register either.
92 */
93 class MemoryNoDisp : public Memory
94 {
95 protected:
96 /// Constructor
97 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
98 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
99 StaticInstPtr _memAccPtr = nullStaticInstPtr)
100 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
101 {
102 }
103
104 std::string
105 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
106 };
107}};
108
109
110output decoder {{
111 std::string
112 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
113 {
114 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
115 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
116 }
117
118 std::string
119 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
120 {
121 return csprintf("%-10s (r%d)", mnemonic, RB);
122 }
123}};
124
125def format LoadAddress(code) {{
126 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
127 header_output = BasicDeclare.subst(iop)
128 decoder_output = BasicConstructor.subst(iop)
129 decode_block = BasicDecode.subst(iop)
130 exec_output = BasicExecute.subst(iop)
131}};
132
133
134def template LoadStoreDeclare {{
135 /**
136 * Static instruction class for "%(mnemonic)s".
137 */
138 class %(class_name)s : public %(base_class)s
139 {
140 protected:
141
142 /**
143 * "Fake" effective address computation class for "%(mnemonic)s".
144 */
145 class EAComp : public %(base_class)s
146 {
147 public:
148 /// Constructor
149 EAComp(ExtMachInst machInst);
150
151 %(BasicExecDeclare)s
152 };
153
154 /**
155 * "Fake" memory access instruction class for "%(mnemonic)s".
156 */
157 class MemAcc : public %(base_class)s
158 {
159 public:
160 /// Constructor
161 MemAcc(ExtMachInst machInst);
162
163 %(BasicExecDeclare)s
164 };
165
166 public:
167
168 /// Constructor.
169 %(class_name)s(ExtMachInst machInst);
170
171 %(BasicExecDeclare)s
172
173 %(InitiateAccDeclare)s
174
175 %(CompleteAccDeclare)s
176 };
177}};
178
179
180def template InitiateAccDeclare {{
181 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
182}};
183
184
185def template CompleteAccDeclare {{
186 Fault completeAcc(Packet *, %(CPU_exec_context)s *,
187 Trace::InstRecord *) const;
188}};
189
190
191def template LoadStoreConstructor {{
192 /** TODO: change op_class to AddrGenOp or something (requires
193 * creating new member of OpClass enum in op_class.hh, updating
194 * config files, etc.). */
195 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
196 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
197 {
198 %(ea_constructor)s;
199 }
200
201 inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
202 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
203 {
204 %(memacc_constructor)s;
205 }
206
207 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
208 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
209 new EAComp(machInst), new MemAcc(machInst))
210 {
211 %(constructor)s;
212 }
213}};
214
215
216def template EACompExecute {{
217 Fault
218 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
219 Trace::InstRecord *traceData) const
220 {
221 Addr EA;
222 Fault fault = NoFault;
223
224 %(fp_enable_check)s;
225 %(op_decl)s;
226 %(op_rd)s;
227 %(code)s;
228
229 if (fault == NoFault) {
230 %(op_wb)s;
231 xc->setEA(EA);
232 }
233
234 return fault;
235 }
236}};
237
238def template LoadMemAccExecute {{
239 Fault
240 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
241 Trace::InstRecord *traceData) const
242 {
243 Addr EA;
244 Fault fault = NoFault;
245
246 %(fp_enable_check)s;
247 %(op_decl)s;
248 %(op_rd)s;
249 EA = xc->getEA();
250
251 if (fault == NoFault) {
252 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
253 %(code)s;
254 }
255
256 if (fault == NoFault) {
257 %(op_wb)s;
258 }
259
260 return fault;
261 }
262}};
263
264
265def template LoadExecute {{
266 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
267 Trace::InstRecord *traceData) const
268 {
269 Addr EA;
270 Fault fault = NoFault;
271
272 %(fp_enable_check)s;
273 %(op_decl)s;
274 %(op_rd)s;
275 %(ea_code)s;
276
277 if (fault == NoFault) {
278 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
279 %(memacc_code)s;
280 }
281
282 if (fault == NoFault) {
283 %(op_wb)s;
284 }
285
286 return fault;
287 }
288}};
289
290
291def template LoadInitiateAcc {{
292 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
293 Trace::InstRecord *traceData) const
294 {
295 Addr EA;
296 Fault fault = NoFault;
297
298 %(fp_enable_check)s;
299 %(op_src_decl)s;
300 %(op_rd)s;
301 %(ea_code)s;
302
303 if (fault == NoFault) {
304 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
305 }
306
307 return fault;
308 }
309}};
310
311
312def template LoadCompleteAcc {{
313 Fault %(class_name)s::completeAcc(Packet *pkt,
314 %(CPU_exec_context)s *xc,
315 Trace::InstRecord *traceData) const
316 {
317 Fault fault = NoFault;
318
319 %(fp_enable_check)s;
320 %(op_decl)s;
321
322 Mem = pkt->get<typeof(Mem)>();
323
324 if (fault == NoFault) {
325 %(memacc_code)s;
326 }
327
328 if (fault == NoFault) {
329 %(op_wb)s;
330 }
331
332 return fault;
333 }
334}};
335
336
337def template StoreMemAccExecute {{
338 Fault
339 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
340 Trace::InstRecord *traceData) const
341 {
342 Addr EA;
343 Fault fault = NoFault;
344 uint64_t write_result = 0;
345
346 %(fp_enable_check)s;
347 %(op_decl)s;
348 %(op_rd)s;
349 EA = xc->getEA();
350
351 if (fault == NoFault) {
352 %(code)s;
353 }
354
355 if (fault == NoFault) {
356 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
357 memAccessFlags, &write_result);
358 if (traceData) { traceData->setData(Mem); }
359 }
360
361 if (fault == NoFault) {
362 %(postacc_code)s;
363 }
364
365 if (fault == NoFault) {
366 %(op_wb)s;
367 }
368
369 return fault;
370 }
371}};
372
373
374def template StoreExecute {{
375 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
376 Trace::InstRecord *traceData) const
377 {
378 Addr EA;
379 Fault fault = NoFault;
380 uint64_t write_result = 0;
381
382 %(fp_enable_check)s;
383 %(op_decl)s;
384 %(op_rd)s;
385 %(ea_code)s;
386
387 if (fault == NoFault) {
388 %(memacc_code)s;
389 }
390
391 if (fault == NoFault) {
392 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
393 memAccessFlags, &write_result);
394 if (traceData) { traceData->setData(Mem); }
395 }
396
397 if (fault == NoFault) {
398 %(postacc_code)s;
399 }
400
401 if (fault == NoFault) {
402 %(op_wb)s;
403 }
404
405 return fault;
406 }
407}};
408
409def template StoreInitiateAcc {{
410 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
411 Trace::InstRecord *traceData) const
412 {
413 Addr EA;
414 Fault fault = NoFault;
415
416 %(fp_enable_check)s;
417 %(op_decl)s;
418 %(op_rd)s;
419 %(ea_code)s;
420
421 if (fault == NoFault) {
422 %(memacc_code)s;
423 }
424
425 if (fault == NoFault) {
426 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
427 memAccessFlags, NULL);
428 if (traceData) { traceData->setData(Mem); }
429 }
430
431 return fault;
432 }
433}};
434
435
436def template StoreCompleteAcc {{
437 Fault %(class_name)s::completeAcc(Packet *pkt,
438 %(CPU_exec_context)s *xc,
439 Trace::InstRecord *traceData) const
440 {
441 Fault fault = NoFault;
442
443 %(fp_enable_check)s;
444 %(op_dest_decl)s;
445
446 if (fault == NoFault) {
447 %(postacc_code)s;
448 }
449
450 if (fault == NoFault) {
451 %(op_wb)s;
452 }
453
454 return fault;
455 }
456}};
457
458
459def template StoreCondCompleteAcc {{
460 Fault %(class_name)s::completeAcc(Packet *pkt,
461 %(CPU_exec_context)s *xc,
462 Trace::InstRecord *traceData) const
463 {
464 Fault fault = NoFault;
465
466 %(fp_enable_check)s;
467 %(op_dest_decl)s;
468
469 uint64_t write_result = pkt->req->getScResult();
470
471 if (fault == NoFault) {
472 %(postacc_code)s;
473 }
474
475 if (fault == NoFault) {
476 %(op_wb)s;
477 }
478
479 return fault;
480 }
481}};
482
483
484def template MiscMemAccExecute {{
485 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
486 Trace::InstRecord *traceData) const
487 {
488 Addr EA;
489 Fault fault = NoFault;
490
491 %(fp_enable_check)s;
492 %(op_decl)s;
493 %(op_rd)s;
494 EA = xc->getEA();
495
496 if (fault == NoFault) {
497 %(code)s;
498 }
499
500 return NoFault;
501 }
502}};
503
504def template MiscExecute {{
505 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
506 Trace::InstRecord *traceData) const
507 {
508 Addr EA;
509 Fault fault = NoFault;
510
511 %(fp_enable_check)s;
512 %(op_decl)s;
513 %(op_rd)s;
514 %(ea_code)s;
515
516 if (fault == NoFault) {
517 %(memacc_code)s;
518 }
519
520 return NoFault;
521 }
522}};
523
524def template MiscInitiateAcc {{
525 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
526 Trace::InstRecord *traceData) const
527 {
528 panic("Misc instruction does not support split access method!");
529 return NoFault;
530 }
531}};
532
533
534def template MiscCompleteAcc {{
535 Fault %(class_name)s::completeAcc(Packet *pkt,
536 %(CPU_exec_context)s *xc,
537 Trace::InstRecord *traceData) const
538 {
539 panic("Misc instruction does not support split access method!");
540
541 return NoFault;
542 }
543}};
544
545// load instructions use Ra as dest, so check for
546// Ra == 31 to detect nops
547def template LoadNopCheckDecode {{
548 {
549 AlphaStaticInst *i = new %(class_name)s(machInst);
550 if (RA == 31) {
551 i = makeNop(i);
552 }
553 return i;
554 }
555}};
556
557
558// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
559def template LoadPrefetchCheckDecode {{
560 {
561 if (RA != 31) {
562 return new %(class_name)s(machInst);
563 }
564 else {
565 return new %(class_name)sPrefetch(machInst);
566 }
567 }
568}};
569
570
571let {{
572def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
573 postacc_code = '', base_class = 'MemoryDisp32',
574 decode_template = BasicDecode, exec_template_base = ''):
575 # Make sure flags are in lists (convert to lists if not).
576 mem_flags = makeList(mem_flags)
577 inst_flags = makeList(inst_flags)
578
579 # add hook to get effective addresses into execution trace output.
580 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
581
582 # generate code block objects
583 ea_cblk = CodeBlock(ea_code)
584 memacc_cblk = CodeBlock(memacc_code)
585 postacc_cblk = CodeBlock(postacc_code)
586
587 # Some CPU models execute the memory operation as an atomic unit,
588 # while others want to separate them into an effective address
589 # computation and a memory access operation. As a result, we need
590 # to generate three StaticInst objects. Note that the latter two
591 # are nested inside the larger "atomic" one.
592
593 # generate InstObjParams for EAComp object
594 ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
595
596 # generate InstObjParams for MemAcc object
597 memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
598 # in the split execution model, the MemAcc portion is responsible
599 # for the post-access code.
600 memacc_iop.postacc_code = postacc_cblk.code
601
602 # generate InstObjParams for InitiateAcc, CompleteAcc object
603 # The code used depends on the template being used
604 if (exec_template_base == 'Load'):
605 initiateacc_cblk = CodeBlock(ea_code + memacc_code)
606 completeacc_cblk = CodeBlock(memacc_code + postacc_code)
607 elif (exec_template_base.startswith('Store')):
608 initiateacc_cblk = CodeBlock(ea_code + memacc_code)
609 completeacc_cblk = CodeBlock(postacc_code)
610 else:
611 initiateacc_cblk = ''
612 completeacc_cblk = ''
613
614 initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
615 inst_flags)
616
617 completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
618 inst_flags)
619
620 if (exec_template_base == 'Load'):
621 initiateacc_iop.ea_code = ea_cblk.code
622 initiateacc_iop.memacc_code = memacc_cblk.code
623 completeacc_iop.memacc_code = memacc_cblk.code
624 completeacc_iop.postacc_code = postacc_cblk.code
625 elif (exec_template_base.startswith('Store')):
626 initiateacc_iop.ea_code = ea_cblk.code
627 initiateacc_iop.memacc_code = memacc_cblk.code
628 completeacc_iop.postacc_code = postacc_cblk.code
629
630 # generate InstObjParams for unified execution
631 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
632 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
633
634 iop.ea_constructor = ea_cblk.constructor
635 iop.ea_code = ea_cblk.code
636 iop.memacc_constructor = memacc_cblk.constructor
637 iop.memacc_code = memacc_cblk.code
638 iop.postacc_code = postacc_cblk.code
639
640 if mem_flags:
641 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
642 iop.constructor += s
643 memacc_iop.constructor += s
644
645 # select templates
646
647 # define aliases... most StoreCond templates are the same as the
648 # corresponding Store templates (only CompleteAcc is different).
649 StoreCondMemAccExecute = StoreMemAccExecute
650 StoreCondExecute = StoreExecute
651 StoreCondInitiateAcc = StoreInitiateAcc
652
653 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
654 fullExecTemplate = eval(exec_template_base + 'Execute')
655 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
656 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
657
658 # (header_output, decoder_output, decode_block, exec_output)
659 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
660 decode_template.subst(iop),
661 EACompExecute.subst(ea_iop)
662 + memAccExecTemplate.subst(memacc_iop)
663 + fullExecTemplate.subst(iop)
664 + initiateAccTemplate.subst(initiateacc_iop)
665 + completeAccTemplate.subst(completeacc_iop))
666}};
667
668
669def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
670 mem_flags = [], inst_flags = []) {{
671 (header_output, decoder_output, decode_block, exec_output) = \
672 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
673 decode_template = LoadNopCheckDecode,
674 exec_template_base = 'Load')
675}};
676
677
678// Note that the flags passed in apply only to the prefetch version
679def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
680 mem_flags = [], pf_flags = [], inst_flags = []) {{
681 # declare the load instruction object and generate the decode block
682 (header_output, decoder_output, decode_block, exec_output) = \
683 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
684 decode_template = LoadPrefetchCheckDecode,
685 exec_template_base = 'Load')
686
687 # Declare the prefetch instruction object.
688
689 # Make sure flag args are lists so we can mess with them.
690 mem_flags = makeList(mem_flags)
691 pf_flags = makeList(pf_flags)
692 inst_flags = makeList(inst_flags)
693
694 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
695 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
696 'IsDataPrefetch', 'MemReadOp']
697
698 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
699 LoadStoreBase(name, Name + 'Prefetch', ea_code,
700 'xc->prefetch(EA, memAccessFlags);',
701 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
702
703 header_output += pf_header_output
704 decoder_output += pf_decoder_output
705 exec_output += pf_exec_output
706}};
707
708
709def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
710 mem_flags = [], inst_flags = []) {{
711 (header_output, decoder_output, decode_block, exec_output) = \
712 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
713 exec_template_base = 'Store')
714}};
715
716
717def format StoreCond(memacc_code, postacc_code,
718 ea_code = {{ EA = Rb + disp; }},
719 mem_flags = [], inst_flags = []) {{
720 (header_output, decoder_output, decode_block, exec_output) = \
721 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
722 postacc_code, exec_template_base = 'StoreCond')
723}};
724
725
726// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
727def format MiscPrefetch(ea_code, memacc_code,
728 mem_flags = [], inst_flags = []) {{
729 (header_output, decoder_output, decode_block, exec_output) = \
730 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
731 base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
732}};
733
734
| 31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions: LoadAddress, Load, Store
35//
36
37output header {{
38 /**
39 * Base class for general Alpha memory-format instructions.
40 */
41 class Memory : public AlphaStaticInst
42 {
43 protected:
44
45 /// Memory request flags. See mem_req_base.hh.
46 unsigned memAccessFlags;
47 /// Pointer to EAComp object.
48 const StaticInstPtr eaCompPtr;
49 /// Pointer to MemAcc object.
50 const StaticInstPtr memAccPtr;
51
52 /// Constructor
53 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
54 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
55 StaticInstPtr _memAccPtr = nullStaticInstPtr)
56 : AlphaStaticInst(mnem, _machInst, __opClass),
57 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
58 {
59 }
60
61 std::string
62 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63
64 public:
65
66 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
67 const StaticInstPtr &memAccInst() const { return memAccPtr; }
68 };
69
70 /**
71 * Base class for memory-format instructions using a 32-bit
72 * displacement (i.e. most of them).
73 */
74 class MemoryDisp32 : public Memory
75 {
76 protected:
77 /// Displacement for EA calculation (signed).
78 int32_t disp;
79
80 /// Constructor.
81 MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
82 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
83 StaticInstPtr _memAccPtr = nullStaticInstPtr)
84 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
85 disp(MEMDISP)
86 {
87 }
88 };
89
90
91 /**
92 * Base class for a few miscellaneous memory-format insts
93 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
94 * None of these instructions has a destination register either.
95 */
96 class MemoryNoDisp : public Memory
97 {
98 protected:
99 /// Constructor
100 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
101 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
102 StaticInstPtr _memAccPtr = nullStaticInstPtr)
103 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
104 {
105 }
106
107 std::string
108 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
109 };
110}};
111
112
113output decoder {{
114 std::string
115 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
116 {
117 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
118 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
119 }
120
121 std::string
122 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
123 {
124 return csprintf("%-10s (r%d)", mnemonic, RB);
125 }
126}};
127
128def format LoadAddress(code) {{
129 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
130 header_output = BasicDeclare.subst(iop)
131 decoder_output = BasicConstructor.subst(iop)
132 decode_block = BasicDecode.subst(iop)
133 exec_output = BasicExecute.subst(iop)
134}};
135
136
137def template LoadStoreDeclare {{
138 /**
139 * Static instruction class for "%(mnemonic)s".
140 */
141 class %(class_name)s : public %(base_class)s
142 {
143 protected:
144
145 /**
146 * "Fake" effective address computation class for "%(mnemonic)s".
147 */
148 class EAComp : public %(base_class)s
149 {
150 public:
151 /// Constructor
152 EAComp(ExtMachInst machInst);
153
154 %(BasicExecDeclare)s
155 };
156
157 /**
158 * "Fake" memory access instruction class for "%(mnemonic)s".
159 */
160 class MemAcc : public %(base_class)s
161 {
162 public:
163 /// Constructor
164 MemAcc(ExtMachInst machInst);
165
166 %(BasicExecDeclare)s
167 };
168
169 public:
170
171 /// Constructor.
172 %(class_name)s(ExtMachInst machInst);
173
174 %(BasicExecDeclare)s
175
176 %(InitiateAccDeclare)s
177
178 %(CompleteAccDeclare)s
179 };
180}};
181
182
183def template InitiateAccDeclare {{
184 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
185}};
186
187
188def template CompleteAccDeclare {{
189 Fault completeAcc(Packet *, %(CPU_exec_context)s *,
190 Trace::InstRecord *) const;
191}};
192
193
194def template LoadStoreConstructor {{
195 /** TODO: change op_class to AddrGenOp or something (requires
196 * creating new member of OpClass enum in op_class.hh, updating
197 * config files, etc.). */
198 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
199 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
200 {
201 %(ea_constructor)s;
202 }
203
204 inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
205 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
206 {
207 %(memacc_constructor)s;
208 }
209
210 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
211 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
212 new EAComp(machInst), new MemAcc(machInst))
213 {
214 %(constructor)s;
215 }
216}};
217
218
219def template EACompExecute {{
220 Fault
221 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
222 Trace::InstRecord *traceData) const
223 {
224 Addr EA;
225 Fault fault = NoFault;
226
227 %(fp_enable_check)s;
228 %(op_decl)s;
229 %(op_rd)s;
230 %(code)s;
231
232 if (fault == NoFault) {
233 %(op_wb)s;
234 xc->setEA(EA);
235 }
236
237 return fault;
238 }
239}};
240
241def template LoadMemAccExecute {{
242 Fault
243 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
244 Trace::InstRecord *traceData) const
245 {
246 Addr EA;
247 Fault fault = NoFault;
248
249 %(fp_enable_check)s;
250 %(op_decl)s;
251 %(op_rd)s;
252 EA = xc->getEA();
253
254 if (fault == NoFault) {
255 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
256 %(code)s;
257 }
258
259 if (fault == NoFault) {
260 %(op_wb)s;
261 }
262
263 return fault;
264 }
265}};
266
267
268def template LoadExecute {{
269 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
270 Trace::InstRecord *traceData) const
271 {
272 Addr EA;
273 Fault fault = NoFault;
274
275 %(fp_enable_check)s;
276 %(op_decl)s;
277 %(op_rd)s;
278 %(ea_code)s;
279
280 if (fault == NoFault) {
281 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
282 %(memacc_code)s;
283 }
284
285 if (fault == NoFault) {
286 %(op_wb)s;
287 }
288
289 return fault;
290 }
291}};
292
293
294def template LoadInitiateAcc {{
295 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
296 Trace::InstRecord *traceData) const
297 {
298 Addr EA;
299 Fault fault = NoFault;
300
301 %(fp_enable_check)s;
302 %(op_src_decl)s;
303 %(op_rd)s;
304 %(ea_code)s;
305
306 if (fault == NoFault) {
307 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
308 }
309
310 return fault;
311 }
312}};
313
314
315def template LoadCompleteAcc {{
316 Fault %(class_name)s::completeAcc(Packet *pkt,
317 %(CPU_exec_context)s *xc,
318 Trace::InstRecord *traceData) const
319 {
320 Fault fault = NoFault;
321
322 %(fp_enable_check)s;
323 %(op_decl)s;
324
325 Mem = pkt->get<typeof(Mem)>();
326
327 if (fault == NoFault) {
328 %(memacc_code)s;
329 }
330
331 if (fault == NoFault) {
332 %(op_wb)s;
333 }
334
335 return fault;
336 }
337}};
338
339
340def template StoreMemAccExecute {{
341 Fault
342 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
343 Trace::InstRecord *traceData) const
344 {
345 Addr EA;
346 Fault fault = NoFault;
347 uint64_t write_result = 0;
348
349 %(fp_enable_check)s;
350 %(op_decl)s;
351 %(op_rd)s;
352 EA = xc->getEA();
353
354 if (fault == NoFault) {
355 %(code)s;
356 }
357
358 if (fault == NoFault) {
359 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
360 memAccessFlags, &write_result);
361 if (traceData) { traceData->setData(Mem); }
362 }
363
364 if (fault == NoFault) {
365 %(postacc_code)s;
366 }
367
368 if (fault == NoFault) {
369 %(op_wb)s;
370 }
371
372 return fault;
373 }
374}};
375
376
377def template StoreExecute {{
378 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
379 Trace::InstRecord *traceData) const
380 {
381 Addr EA;
382 Fault fault = NoFault;
383 uint64_t write_result = 0;
384
385 %(fp_enable_check)s;
386 %(op_decl)s;
387 %(op_rd)s;
388 %(ea_code)s;
389
390 if (fault == NoFault) {
391 %(memacc_code)s;
392 }
393
394 if (fault == NoFault) {
395 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
396 memAccessFlags, &write_result);
397 if (traceData) { traceData->setData(Mem); }
398 }
399
400 if (fault == NoFault) {
401 %(postacc_code)s;
402 }
403
404 if (fault == NoFault) {
405 %(op_wb)s;
406 }
407
408 return fault;
409 }
410}};
411
412def template StoreInitiateAcc {{
413 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
414 Trace::InstRecord *traceData) const
415 {
416 Addr EA;
417 Fault fault = NoFault;
418
419 %(fp_enable_check)s;
420 %(op_decl)s;
421 %(op_rd)s;
422 %(ea_code)s;
423
424 if (fault == NoFault) {
425 %(memacc_code)s;
426 }
427
428 if (fault == NoFault) {
429 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
430 memAccessFlags, NULL);
431 if (traceData) { traceData->setData(Mem); }
432 }
433
434 return fault;
435 }
436}};
437
438
439def template StoreCompleteAcc {{
440 Fault %(class_name)s::completeAcc(Packet *pkt,
441 %(CPU_exec_context)s *xc,
442 Trace::InstRecord *traceData) const
443 {
444 Fault fault = NoFault;
445
446 %(fp_enable_check)s;
447 %(op_dest_decl)s;
448
449 if (fault == NoFault) {
450 %(postacc_code)s;
451 }
452
453 if (fault == NoFault) {
454 %(op_wb)s;
455 }
456
457 return fault;
458 }
459}};
460
461
462def template StoreCondCompleteAcc {{
463 Fault %(class_name)s::completeAcc(Packet *pkt,
464 %(CPU_exec_context)s *xc,
465 Trace::InstRecord *traceData) const
466 {
467 Fault fault = NoFault;
468
469 %(fp_enable_check)s;
470 %(op_dest_decl)s;
471
472 uint64_t write_result = pkt->req->getScResult();
473
474 if (fault == NoFault) {
475 %(postacc_code)s;
476 }
477
478 if (fault == NoFault) {
479 %(op_wb)s;
480 }
481
482 return fault;
483 }
484}};
485
486
487def template MiscMemAccExecute {{
488 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
489 Trace::InstRecord *traceData) const
490 {
491 Addr EA;
492 Fault fault = NoFault;
493
494 %(fp_enable_check)s;
495 %(op_decl)s;
496 %(op_rd)s;
497 EA = xc->getEA();
498
499 if (fault == NoFault) {
500 %(code)s;
501 }
502
503 return NoFault;
504 }
505}};
506
507def template MiscExecute {{
508 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
509 Trace::InstRecord *traceData) const
510 {
511 Addr EA;
512 Fault fault = NoFault;
513
514 %(fp_enable_check)s;
515 %(op_decl)s;
516 %(op_rd)s;
517 %(ea_code)s;
518
519 if (fault == NoFault) {
520 %(memacc_code)s;
521 }
522
523 return NoFault;
524 }
525}};
526
527def template MiscInitiateAcc {{
528 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
529 Trace::InstRecord *traceData) const
530 {
531 panic("Misc instruction does not support split access method!");
532 return NoFault;
533 }
534}};
535
536
537def template MiscCompleteAcc {{
538 Fault %(class_name)s::completeAcc(Packet *pkt,
539 %(CPU_exec_context)s *xc,
540 Trace::InstRecord *traceData) const
541 {
542 panic("Misc instruction does not support split access method!");
543
544 return NoFault;
545 }
546}};
547
548// load instructions use Ra as dest, so check for
549// Ra == 31 to detect nops
550def template LoadNopCheckDecode {{
551 {
552 AlphaStaticInst *i = new %(class_name)s(machInst);
553 if (RA == 31) {
554 i = makeNop(i);
555 }
556 return i;
557 }
558}};
559
560
561// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
562def template LoadPrefetchCheckDecode {{
563 {
564 if (RA != 31) {
565 return new %(class_name)s(machInst);
566 }
567 else {
568 return new %(class_name)sPrefetch(machInst);
569 }
570 }
571}};
572
573
574let {{
575def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
576 postacc_code = '', base_class = 'MemoryDisp32',
577 decode_template = BasicDecode, exec_template_base = ''):
578 # Make sure flags are in lists (convert to lists if not).
579 mem_flags = makeList(mem_flags)
580 inst_flags = makeList(inst_flags)
581
582 # add hook to get effective addresses into execution trace output.
583 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
584
585 # generate code block objects
586 ea_cblk = CodeBlock(ea_code)
587 memacc_cblk = CodeBlock(memacc_code)
588 postacc_cblk = CodeBlock(postacc_code)
589
590 # Some CPU models execute the memory operation as an atomic unit,
591 # while others want to separate them into an effective address
592 # computation and a memory access operation. As a result, we need
593 # to generate three StaticInst objects. Note that the latter two
594 # are nested inside the larger "atomic" one.
595
596 # generate InstObjParams for EAComp object
597 ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
598
599 # generate InstObjParams for MemAcc object
600 memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
601 # in the split execution model, the MemAcc portion is responsible
602 # for the post-access code.
603 memacc_iop.postacc_code = postacc_cblk.code
604
605 # generate InstObjParams for InitiateAcc, CompleteAcc object
606 # The code used depends on the template being used
607 if (exec_template_base == 'Load'):
608 initiateacc_cblk = CodeBlock(ea_code + memacc_code)
609 completeacc_cblk = CodeBlock(memacc_code + postacc_code)
610 elif (exec_template_base.startswith('Store')):
611 initiateacc_cblk = CodeBlock(ea_code + memacc_code)
612 completeacc_cblk = CodeBlock(postacc_code)
613 else:
614 initiateacc_cblk = ''
615 completeacc_cblk = ''
616
617 initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
618 inst_flags)
619
620 completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
621 inst_flags)
622
623 if (exec_template_base == 'Load'):
624 initiateacc_iop.ea_code = ea_cblk.code
625 initiateacc_iop.memacc_code = memacc_cblk.code
626 completeacc_iop.memacc_code = memacc_cblk.code
627 completeacc_iop.postacc_code = postacc_cblk.code
628 elif (exec_template_base.startswith('Store')):
629 initiateacc_iop.ea_code = ea_cblk.code
630 initiateacc_iop.memacc_code = memacc_cblk.code
631 completeacc_iop.postacc_code = postacc_cblk.code
632
633 # generate InstObjParams for unified execution
634 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
635 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
636
637 iop.ea_constructor = ea_cblk.constructor
638 iop.ea_code = ea_cblk.code
639 iop.memacc_constructor = memacc_cblk.constructor
640 iop.memacc_code = memacc_cblk.code
641 iop.postacc_code = postacc_cblk.code
642
643 if mem_flags:
644 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
645 iop.constructor += s
646 memacc_iop.constructor += s
647
648 # select templates
649
650 # define aliases... most StoreCond templates are the same as the
651 # corresponding Store templates (only CompleteAcc is different).
652 StoreCondMemAccExecute = StoreMemAccExecute
653 StoreCondExecute = StoreExecute
654 StoreCondInitiateAcc = StoreInitiateAcc
655
656 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
657 fullExecTemplate = eval(exec_template_base + 'Execute')
658 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
659 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
660
661 # (header_output, decoder_output, decode_block, exec_output)
662 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
663 decode_template.subst(iop),
664 EACompExecute.subst(ea_iop)
665 + memAccExecTemplate.subst(memacc_iop)
666 + fullExecTemplate.subst(iop)
667 + initiateAccTemplate.subst(initiateacc_iop)
668 + completeAccTemplate.subst(completeacc_iop))
669}};
670
671
672def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
673 mem_flags = [], inst_flags = []) {{
674 (header_output, decoder_output, decode_block, exec_output) = \
675 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
676 decode_template = LoadNopCheckDecode,
677 exec_template_base = 'Load')
678}};
679
680
681// Note that the flags passed in apply only to the prefetch version
682def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
683 mem_flags = [], pf_flags = [], inst_flags = []) {{
684 # declare the load instruction object and generate the decode block
685 (header_output, decoder_output, decode_block, exec_output) = \
686 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
687 decode_template = LoadPrefetchCheckDecode,
688 exec_template_base = 'Load')
689
690 # Declare the prefetch instruction object.
691
692 # Make sure flag args are lists so we can mess with them.
693 mem_flags = makeList(mem_flags)
694 pf_flags = makeList(pf_flags)
695 inst_flags = makeList(inst_flags)
696
697 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
698 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
699 'IsDataPrefetch', 'MemReadOp']
700
701 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
702 LoadStoreBase(name, Name + 'Prefetch', ea_code,
703 'xc->prefetch(EA, memAccessFlags);',
704 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
705
706 header_output += pf_header_output
707 decoder_output += pf_decoder_output
708 exec_output += pf_exec_output
709}};
710
711
712def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
713 mem_flags = [], inst_flags = []) {{
714 (header_output, decoder_output, decode_block, exec_output) = \
715 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
716 exec_template_base = 'Store')
717}};
718
719
720def format StoreCond(memacc_code, postacc_code,
721 ea_code = {{ EA = Rb + disp; }},
722 mem_flags = [], inst_flags = []) {{
723 (header_output, decoder_output, decode_block, exec_output) = \
724 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
725 postacc_code, exec_template_base = 'StoreCond')
726}};
727
728
729// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
730def format MiscPrefetch(ea_code, memacc_code,
731 mem_flags = [], inst_flags = []) {{
732 (header_output, decoder_output, decode_block, exec_output) = \
733 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
734 base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
735}};
736
737
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