1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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60
61 std::string
62 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
63
64 public:
65
66 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
67 const StaticInstPtr &memAccInst() const { return memAccPtr; }
68
69 Request::Flags memAccFlags() { return memAccessFlags; }
70 };
71
72 /**
73 * Base class for memory-format instructions using a 32-bit
74 * displacement (i.e. most of them).
75 */
76 class MemoryDisp32 : public Memory
77 {

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173 /// Constructor.
174 %(class_name)s(ExtMachInst machInst);
175
176 %(BasicExecDeclare)s
177
178 %(InitiateAccDeclare)s
179
180 %(CompleteAccDeclare)s
181
182 %(MemAccSizeDeclare)s
183 };
184}};
185
186
187def template InitiateAccDeclare {{
188 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
189}};
190
191
192def template CompleteAccDeclare {{
193 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
194 Trace::InstRecord *) const;
195}};
196
197def template MemAccSizeDeclare {{
198 int memAccSize(%(CPU_exec_context)s *xc);
199}};
200
201def template MiscMemAccSize {{
202 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
203 {
204 panic("Misc instruction does not support split access method!");
205 return 0;
206 }
207}};
208
209def template LoadStoreMemAccSize {{
210 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
211 {
212 // Return the memory access size in bytes
213 return (%(mem_acc_size)d / 8);
214 }
215}};
216
217def template EACompConstructor {{
218 /** TODO: change op_class to AddrGenOp or something (requires
219 * creating new member of OpClass enum in op_class.hh, updating
220 * config files, etc.). */
221 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
222 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
223 {
224 %(constructor)s;

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638 Trace::InstRecord *traceData) const
639 {
640 warn("Misc instruction does not support split access method!");
641
642 return NoFault;
643 }
644}};
645
646def template MiscMemAccSize {{
647 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
648 {
649 panic("Misc instruction does not support split access method!");
650 return 0;
651 }
652}};
653
654// load instructions use Ra as dest, so check for
655// Ra == 31 to detect nops
656def template LoadNopCheckDecode {{
657 {
658 AlphaStaticInst *i = new %(class_name)s(machInst);
659 if (RA == 31) {
660 i = makeNop(i);
661 }

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719 # corresponding Store template..
720 StoreCondInitiateAcc = StoreInitiateAcc
721
722 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
723 fullExecTemplate = eval(exec_template_base + 'Execute')
724 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
725 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
726
727 if (exec_template_base == 'Load' or exec_template_base == 'Store'):
728 memAccSizeTemplate = eval('LoadStoreMemAccSize')
729 else:
730 memAccSizeTemplate = eval('MiscMemAccSize')
731
732 # (header_output, decoder_output, decode_block, exec_output)
733 return (LoadStoreDeclare.subst(iop),
734 EACompConstructor.subst(ea_iop)
735 + MemAccConstructor.subst(memacc_iop)
736 + LoadStoreConstructor.subst(iop),
737 decode_template.subst(iop),
738 EACompExecute.subst(ea_iop)
739 + memAccExecTemplate.subst(memacc_iop)
740 + fullExecTemplate.subst(iop)
741 + initiateAccTemplate.subst(iop)
742 + completeAccTemplate.subst(iop)
743 + memAccSizeTemplate.subst(memacc_iop))
744}};
745
746def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
747 mem_flags = [], inst_flags = []) {{
748 (header_output, decoder_output, decode_block, exec_output) = \
749 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
750 decode_template = LoadNopCheckDecode,
751 exec_template_base = 'Load')

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