1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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121 std::string
122 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
123 {
124 return csprintf("%-10s (r%d)", mnemonic, RB);
125 }
126}};
127
128def format LoadAddress(code) {{
129 iop = InstObjParams(name, Name, 'MemoryDisp32', code)
130 header_output = BasicDeclare.subst(iop)
131 decoder_output = BasicConstructor.subst(iop)
132 decode_block = BasicDecode.subst(iop)
133 exec_output = BasicExecute.subst(iop)
134}};
135
136
137def template LoadStoreDeclare {{

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186
187
188def template CompleteAccDeclare {{
189 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
190 Trace::InstRecord *) const;
191}};
192
193
194def template EACompConstructor {{
195 /** TODO: change op_class to AddrGenOp or something (requires
196 * creating new member of OpClass enum in op_class.hh, updating
197 * config files, etc.). */
198 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
199 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
200 {
201 %(constructor)s;
202 }
203}};
204
205
206def template MemAccConstructor {{
207 inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
208 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
209 {
210 %(constructor)s;
211 }
212}};
213
214
215def template LoadStoreConstructor {{
216 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
217 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
218 new EAComp(machInst), new MemAcc(machInst))
219 {
220 %(constructor)s;
221 }
222}};
223

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228 Trace::InstRecord *traceData) const
229 {
230 Addr EA;
231 Fault fault = NoFault;
232
233 %(fp_enable_check)s;
234 %(op_decl)s;
235 %(op_rd)s;
236 %(ea_code)s;
237
238 if (fault == NoFault) {
239 %(op_wb)s;
240 xc->setEA(EA);
241 }
242
243 return fault;
244 }

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254
255 %(fp_enable_check)s;
256 %(op_decl)s;
257 %(op_rd)s;
258 EA = xc->getEA();
259
260 if (fault == NoFault) {
261 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
262 %(memacc_code)s;
263 }
264
265 if (fault == NoFault) {
266 %(op_wb)s;
267 }
268
269 return fault;
270 }

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353 uint64_t write_result = 0;
354
355 %(fp_enable_check)s;
356 %(op_decl)s;
357 %(op_rd)s;
358 EA = xc->getEA();
359
360 if (fault == NoFault) {
361 %(memacc_code)s;
362 }
363
364 if (fault == NoFault) {
365 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
366 memAccessFlags, &write_result);
367 if (traceData) { traceData->setData(Mem); }
368 }
369

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498 Fault fault = NoFault;
499
500 %(fp_enable_check)s;
501 %(op_decl)s;
502 %(op_rd)s;
503 EA = xc->getEA();
504
505 if (fault == NoFault) {
506 %(memacc_code)s;
507 }
508
509 return NoFault;
510 }
511}};
512
513def template MiscExecute {{
514 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,

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583 decode_template = BasicDecode, exec_template_base = ''):
584 # Make sure flags are in lists (convert to lists if not).
585 mem_flags = makeList(mem_flags)
586 inst_flags = makeList(inst_flags)
587
588 # add hook to get effective addresses into execution trace output.
589 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
590
591 # Some CPU models execute the memory operation as an atomic unit,
592 # while others want to separate them into an effective address
593 # computation and a memory access operation. As a result, we need
594 # to generate three StaticInst objects. Note that the latter two
595 # are nested inside the larger "atomic" one.
596
597 # Generate InstObjParams for each of the three objects. Note that
598 # they differ only in the set of code objects contained (which in
599 # turn affects the object's overall operand list).
600 iop = InstObjParams(name, Name, base_class,
601 { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
602 inst_flags)
603 ea_iop = InstObjParams(name, Name, base_class,
604 { 'ea_code':ea_code },
605 inst_flags)
606 memacc_iop = InstObjParams(name, Name, base_class,
607 { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
608 inst_flags)
609
610 if mem_flags:
611 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
612 iop.constructor += s
613 memacc_iop.constructor += s
614
615 # select templates
616
617 # define aliases... most StoreCond templates are the same as the
618 # corresponding Store templates (only CompleteAcc is different).
619 StoreCondMemAccExecute = StoreMemAccExecute
620 StoreCondExecute = StoreExecute
621 StoreCondInitiateAcc = StoreInitiateAcc
622
623 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
624 fullExecTemplate = eval(exec_template_base + 'Execute')
625 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
626 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
627
628 # (header_output, decoder_output, decode_block, exec_output)
629 return (LoadStoreDeclare.subst(iop),
630 EACompConstructor.subst(ea_iop)
631 + MemAccConstructor.subst(memacc_iop)
632 + LoadStoreConstructor.subst(iop),
633 decode_template.subst(iop),
634 EACompExecute.subst(ea_iop)
635 + memAccExecTemplate.subst(memacc_iop)
636 + fullExecTemplate.subst(iop)
637 + initiateAccTemplate.subst(iop)
638 + completeAccTemplate.subst(iop))
639}};
640
641def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
642 mem_flags = [], inst_flags = []) {{
643 (header_output, decoder_output, decode_block, exec_output) = \
644 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
645 decode_template = LoadNopCheckDecode,
646 exec_template_base = 'Load')

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