main.isa (7794:8a7ba5a1b35d) main.isa (7799:5d0f62927d75)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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97
98////////////////////////////////////////////////////////////////////
99//
100// Bitfield definitions.
101//
102
103// Universal (format-independent) fields
104def bitfield PALMODE <32:32>;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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97
98////////////////////////////////////////////////////////////////////
99//
100// Bitfield definitions.
101//
102
103// Universal (format-independent) fields
104def bitfield PALMODE <32:32>;
105def bitfield OPCODE <31:26>;
106def bitfield RA <25:21>;
107def bitfield RB <20:16>;
105def bitfield OPCODE <31:26>;
106def bitfield RA <25:21>;
107def bitfield RB <20:16>;
108
109// Memory format
110def signed bitfield MEMDISP <15: 0>; // displacement
111def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
112
113// Memory-format jumps
108
109// Memory format
110def signed bitfield MEMDISP <15: 0>; // displacement
111def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
112
113// Memory-format jumps
114def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
115def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
114def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
115def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
116
117// Branch format
118def signed bitfield BRDISP <20: 0>; // displacement
119
120// Integer operate format(s>;
116
117// Branch format
118def signed bitfield BRDISP <20: 0>; // displacement
119
120// Integer operate format(s>;
121def bitfield INTIMM <20:13>; // integer immediate (literal)
122def bitfield IMM <12:12>; // immediate flag
123def bitfield INTFUNC <11: 5>; // function code
124def bitfield RC < 4: 0>; // dest reg
121def bitfield INTIMM <20:13>; // integer immediate (literal)
122def bitfield IMM <12:12>; // immediate flag
123def bitfield INTFUNC <11: 5>; // function code
124def bitfield RC < 4: 0>; // dest reg
125
126// Floating-point operate format
125
126// Floating-point operate format
127def bitfield FA <25:21>;
128def bitfield FB <20:16>;
127def bitfield FA <25:21>;
128def bitfield FB <20:16>;
129def bitfield FP_FULLFUNC <15: 5>; // complete function code
130 def bitfield FP_TRAPMODE <15:13>; // trapping mode
131 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
132 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
133 def bitfield FP_SRCTYPE <10: 9>; // source reg type
134 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
135 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
129def bitfield FP_FULLFUNC <15: 5>; // complete function code
130 def bitfield FP_TRAPMODE <15:13>; // trapping mode
131 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
132 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
133 def bitfield FP_SRCTYPE <10: 9>; // source reg type
134 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
135 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
136def bitfield FC < 4: 0>; // dest reg
136def bitfield FC < 4: 0>; // dest reg
137
138// PALcode format
137
138// PALcode format
139def bitfield PALFUNC <25: 0>; // function code
139def bitfield PALFUNC <25: 0>; // function code
140
141// EV5 PAL instructions:
142// HW_LD/HW_ST
143def bitfield HW_LDST_PHYS <15>; // address is physical
144def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
145def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
146def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
147def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
148def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
149def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
150def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
151
152// HW_REI
153def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
154def bitfield HW_REI_MBZ <13: 0>; // must be zero
155
156// HW_MTPR/MW_MFPR
140
141// EV5 PAL instructions:
142// HW_LD/HW_ST
143def bitfield HW_LDST_PHYS <15>; // address is physical
144def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
145def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
146def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
147def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
148def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
149def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
150def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
151
152// HW_REI
153def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
154def bitfield HW_REI_MBZ <13: 0>; // must be zero
155
156// HW_MTPR/MW_MFPR
157def bitfield HW_IPR_IDX <15:0>; // IPR index
157def bitfield HW_IPR_IDX <15:0>; // IPR index
158
159// M5 instructions
160def bitfield M5FUNC <7:0>;
161
162def operand_types {{
163 'sb' : ('signed int', 8),
164 'ub' : ('unsigned int', 8),
165 'sw' : ('signed int', 16),

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158
159// M5 instructions
160def bitfield M5FUNC <7:0>;
161
162def operand_types {{
163 'sb' : ('signed int', 8),
164 'ub' : ('unsigned int', 8),
165 'sw' : ('signed int', 16),

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