main.isa (5640:c811ced9efc1) main.isa (5702:bf84e2fa05f7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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64
65using namespace AlphaISA;
66}};
67
68output exec {{
69#include <math.h>
70
71#if FULL_SYSTEM
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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64
65using namespace AlphaISA;
66}};
67
68output exec {{
69#include <math.h>
70
71#if FULL_SYSTEM
72#include "arch/alpha/kernel_stats.hh"
73#include "arch/alpha/osfpal.hh"
74#include "sim/pseudo_inst.hh"
75#endif
76#include "arch/alpha/ipr.hh"
77#include "base/fenv.hh"
78#include "config/ss_compatible_fp.hh"
79#include "cpu/base.hh"
80#include "cpu/exetrace.hh"
81#include "mem/packet.hh"

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184 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
185 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
186 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
187 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
188 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
189 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
190 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
191 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
72#include "sim/pseudo_inst.hh"
73#endif
74#include "arch/alpha/ipr.hh"
75#include "base/fenv.hh"
76#include "config/ss_compatible_fp.hh"
77#include "cpu/base.hh"
78#include "cpu/exetrace.hh"
79#include "mem/packet.hh"

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182 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
183 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
184 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
185 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
186 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
187 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
188 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
189 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
192 'ExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
193 # The next two are hacks for non-full-system call-pal emulation
194 'R0': ('IntReg', 'uq', '0', None, 1),
195 'R16': ('IntReg', 'uq', '16', None, 1),
196 'R17': ('IntReg', 'uq', '17', None, 1),
197 'R18': ('IntReg', 'uq', '18', None, 1)
198}};
199
200////////////////////////////////////////////////////////////////////

--- 265 unchanged lines hidden --- 		190 # The next two are hacks for non-full-system call-pal emulation
191 'R0': ('IntReg', 'uq', '0', None, 1),
192 'R16': ('IntReg', 'uq', '16', None, 1),
193 'R17': ('IntReg', 'uq', '17', None, 1),
194 'R18': ('IntReg', 'uq', '18', None, 1)
195}};
196
197////////////////////////////////////////////////////////////////////

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