| main.isa (3953:300d526414e6) | main.isa (5568:d14250d688d2) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 159 unchanged lines hidden (view full) --- 168 'sf' : ('float', 32), 169 'df' : ('float', 64) 170}}; 171 172def operands {{ 173 # Int regs default to unsigned, but code should not count on this. 174 # For clarity, descriptions that depend on unsigned behavior should 175 # explicitly specify '.uq'. | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 159 unchanged lines hidden (view full) --- 168 'sf' : ('float', 32), 169 'df' : ('float', 64) 170}}; 171 172def operands {{ 173 # Int regs default to unsigned, but code should not count on this. 174 # For clarity, descriptions that depend on unsigned behavior should 175 # explicitly specify '.uq'. |
| 176 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA', | 176 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', |
| 177 'IsInteger', 1), | 177 'IsInteger', 1), |
| 178 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB', | 178 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', |
| 179 'IsInteger', 2), | 179 'IsInteger', 2), |
| 180 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC', | 180 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC', |
| 181 'IsInteger', 3), 182 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 183 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 184 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 185 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 186 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), 187 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 188 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), --- 274 unchanged lines hidden --- | 181 'IsInteger', 3), 182 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 183 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 184 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 185 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 186 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), 187 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 188 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), --- 274 unchanged lines hidden --- |