main.isa (12236:126ac9da6050) main.isa (12614:0bc465e1f5fb)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh" // some constructors use MemReq flags
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh" // some constructors use MemReq flags
54#include "sim/byteswap.hh"
55
54}};
55
56output decoder {{
57#include <cmath>
58
59#include "arch/alpha/decoder.hh"
60#include "arch/alpha/registers.hh"
61#include "arch/alpha/regredir.hh"
56}};
57
58output decoder {{
59#include <cmath>
60
61#include "arch/alpha/decoder.hh"
62#include "arch/alpha/registers.hh"
63#include "arch/alpha/regredir.hh"
62#include "base/loader/symtab.hh"
63#include "base/cprintf.hh"
64#include "base/fenv.hh"
64#include "base/cprintf.hh"
65#include "base/fenv.hh"
66#include "base/loader/symtab.hh"
65#include "config/ss_compatible_fp.hh"
66#include "cpu/thread_context.hh" // for Jump::branchTarget()
67#include "mem/packet.hh"
68#include "sim/full_system.hh"
69
70using namespace AlphaISA;
71}};
72

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214// #define SS_COMPATIBLE_DISASSEMBLY
215
216 /**
217 * Base class for all Alpha static instructions.
218 */
219 class AlphaStaticInst : public StaticInst
220 {
221 protected:
67#include "config/ss_compatible_fp.hh"
68#include "cpu/thread_context.hh" // for Jump::branchTarget()
69#include "mem/packet.hh"
70#include "sim/full_system.hh"
71
72using namespace AlphaISA;
73}};
74

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216// #define SS_COMPATIBLE_DISASSEMBLY
217
218 /**
219 * Base class for all Alpha static instructions.
220 */
221 class AlphaStaticInst : public StaticInst
222 {
223 protected:
222
223 /// Constructor.
224 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
225 OpClass __opClass)
226 : StaticInst(mnem, _machInst, __opClass)
227 {
228 }
229
230 /// Print a register name for disassembly given the unique
231 /// dependence tag number (FP or int).
232 void printReg(std::ostream &os, RegId reg) const;
233
234 std::string
235 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
236
237 void
238 advancePC(AlphaISA::PCState &pcState) const
239 {
240 pcState.advance();
241 }
224 /// Constructor.
225 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
226 OpClass __opClass)
227 : StaticInst(mnem, _machInst, __opClass)
228 {
229 }
230
231 /// Print a register name for disassembly given the unique
232 /// dependence tag number (FP or int).
233 void printReg(std::ostream &os, RegId reg) const;
234
235 std::string
236 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
237
238 void
239 advancePC(AlphaISA::PCState &pcState) const
240 {
241 pcState.advance();
242 }
243
244 public:
245 size_t
246 asBytes(void *buf, size_t max_size) override
247 {
248 return simpleAsBytes(buf, max_size, machInst);
249 }
242 };
243}};
244
245output decoder {{
246 void
247 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
248 {
249 if (reg.isIntReg()) {

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251}};
252
253output decoder {{
254 void
255 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
256 {
257 if (reg.isIntReg()) {

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