79 80using namespace AlphaISA; 81}}; 82 83//////////////////////////////////////////////////////////////////// 84// 85// Namespace statement. Everything below this line will be in the 86// AlphaISAInst namespace. 87// 88 89 90namespace AlphaISA; 91 92//////////////////////////////////////////////////////////////////// 93// 94// Bitfield definitions. 95// 96 97// Universal (format-independent) fields 98def bitfield PALMODE <32:32>; 99def bitfield OPCODE <31:26>; 100def bitfield RA <25:21>; 101def bitfield RB <20:16>; 102 103// Memory format 104def signed bitfield MEMDISP <15: 0>; // displacement 105def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) 106 107// Memory-format jumps 108def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) 109def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) 110 111// Branch format 112def signed bitfield BRDISP <20: 0>; // displacement 113 114// Integer operate format(s>; 115def bitfield INTIMM <20:13>; // integer immediate (literal) 116def bitfield IMM <12:12>; // immediate flag 117def bitfield INTFUNC <11: 5>; // function code 118def bitfield RC < 4: 0>; // dest reg 119 120// Floating-point operate format 121def bitfield FA <25:21>; 122def bitfield FB <20:16>; 123def bitfield FP_FULLFUNC <15: 5>; // complete function code 124 def bitfield FP_TRAPMODE <15:13>; // trapping mode 125 def bitfield FP_ROUNDMODE <12:11>; // rounding mode 126 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding 127 def bitfield FP_SRCTYPE <10: 9>; // source reg type 128 def bitfield FP_SHORTFUNC < 8: 5>; // short function code 129 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code 130def bitfield FC < 4: 0>; // dest reg 131 132// PALcode format 133def bitfield PALFUNC <25: 0>; // function code 134 135// EV5 PAL instructions: 136// HW_LD/HW_ST 137def bitfield HW_LDST_PHYS <15>; // address is physical 138def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR 139def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc 140def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b 141def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch 142def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked 143def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional 144def signed bitfield HW_LDST_DISP <9:0>; // signed displacement 145 146// HW_REI 147def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk 148def bitfield HW_REI_MBZ <13: 0>; // must be zero 149 150// HW_MTPR/MW_MFPR 151def bitfield HW_IPR_IDX <15:0>; // IPR index 152 153// M5 instructions 154def bitfield M5FUNC <7:0>; 155 156def operand_types {{ 157 'sb' : ('signed int', 8), 158 'ub' : ('unsigned int', 8), 159 'sw' : ('signed int', 16), 160 'uw' : ('unsigned int', 16), 161 'sl' : ('signed int', 32), 162 'ul' : ('unsigned int', 32), 163 'sq' : ('signed int', 64), 164 'uq' : ('unsigned int', 64), 165 'sf' : ('float', 32), 166 'df' : ('float', 64) 167}}; 168 169def operands {{ 170 # Int regs default to unsigned, but code should not count on this. 171 # For clarity, descriptions that depend on unsigned behavior should 172 # explicitly specify '.uq'. 173 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA', 174 'IsInteger', 1), 175 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB', 176 'IsInteger', 2), 177 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC', 178 'IsInteger', 3), 179 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 180 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 181 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 182 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 183 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), 184 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1), 185 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1), 186 # The next two are hacks for non-full-system call-pal emulation 187 'R0': ('IntReg', 'uq', '0', None, 1), 188 'R16': ('IntReg', 'uq', '16', None, 1), 189 'R17': ('IntReg', 'uq', '17', None, 1), 190 'R18': ('IntReg', 'uq', '18', None, 1) 191}}; 192 193//////////////////////////////////////////////////////////////////// 194// 195// Basic instruction classes/templates/formats etc. 196// 197 198output header {{ 199// uncomment the following to get SimpleScalar-compatible disassembly 200// (useful for diffing output traces). 201// #define SS_COMPATIBLE_DISASSEMBLY 202 203 /** 204 * Base class for all Alpha static instructions. 205 */ 206 class AlphaStaticInst : public StaticInst 207 { 208 protected: 209 210 /// Make AlphaISA register dependence tags directly visible in 211 /// this class and derived classes. Maybe these should really 212 /// live here and not in the AlphaISA namespace. 213 enum DependenceTags { 214 FP_Base_DepTag = AlphaISA::FP_Base_DepTag, 215 Fpcr_DepTag = AlphaISA::Fpcr_DepTag, 216 Uniq_DepTag = AlphaISA::Uniq_DepTag, 217 Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag, 218 Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag, 219 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag 220 }; 221 222 /// Constructor. 223 AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 224 OpClass __opClass) 225 : StaticInst(mnem, _machInst, __opClass) 226 { 227 } 228 229 /// Print a register name for disassembly given the unique 230 /// dependence tag number (FP or int). 231 void printReg(std::ostream &os, int reg) const; 232 233 std::string 234 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 235 }; 236}}; 237 238output decoder {{ 239 void 240 AlphaStaticInst::printReg(std::ostream &os, int reg) const 241 { 242 if (reg < FP_Base_DepTag) { 243 ccprintf(os, "r%d", reg); 244 } 245 else { 246 ccprintf(os, "f%d", reg - FP_Base_DepTag); 247 } 248 } 249 250 std::string 251 AlphaStaticInst::generateDisassembly(Addr pc, 252 const SymbolTable *symtab) const 253 { 254 std::stringstream ss; 255 256 ccprintf(ss, "%-10s ", mnemonic); 257 258 // just print the first two source regs... if there's 259 // a third one, it's a read-modify-write dest (Rc), 260 // e.g. for CMOVxx 261 if (_numSrcRegs > 0) { 262 printReg(ss, _srcRegIdx[0]); 263 } 264 if (_numSrcRegs > 1) { 265 ss << ","; 266 printReg(ss, _srcRegIdx[1]); 267 } 268 269 // just print the first dest... if there's a second one, 270 // it's generally implicit 271 if (_numDestRegs > 0) { 272 if (_numSrcRegs > 0) 273 ss << ","; 274 printReg(ss, _destRegIdx[0]); 275 } 276 277 return ss.str(); 278 } 279}}; 280 281// Declarations for execute() methods. 282def template BasicExecDeclare {{ 283 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; 284}}; 285 286// Basic instruction class declaration template. 287def template BasicDeclare {{ 288 /** 289 * Static instruction class for "%(mnemonic)s". 290 */ 291 class %(class_name)s : public %(base_class)s 292 { 293 public: 294 /// Constructor. 295 %(class_name)s(ExtMachInst machInst); 296 297 %(BasicExecDeclare)s 298 }; 299}}; 300 301// Basic instruction class constructor template. 302def template BasicConstructor {{ 303 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 305 { 306 %(constructor)s; 307 } 308}}; 309 310// Basic instruction class execute method template. 311def template BasicExecute {{ 312 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 313 Trace::InstRecord *traceData) const 314 { 315 Fault fault = NoFault; 316 317 %(fp_enable_check)s; 318 %(op_decl)s; 319 %(op_rd)s; 320 %(code)s; 321 322 if (fault == NoFault) { 323 %(op_wb)s; 324 } 325 326 return fault; 327 } 328}}; 329 330// Basic decode template. 331def template BasicDecode {{ 332 return new %(class_name)s(machInst); 333}}; 334 335// Basic decode template, passing mnemonic in as string arg to constructor. 336def template BasicDecodeWithMnemonic {{ 337 return new %(class_name)s("%(mnemonic)s", machInst); 338}}; 339 340// The most basic instruction format... used only for a few misc. insts 341def format BasicOperate(code, *flags) {{ 342 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags) 343 header_output = BasicDeclare.subst(iop) 344 decoder_output = BasicConstructor.subst(iop) 345 decode_block = BasicDecode.subst(iop) 346 exec_output = BasicExecute.subst(iop) 347}}; 348 349 350 351//////////////////////////////////////////////////////////////////// 352// 353// Nop 354// 355 356output header {{ 357 /** 358 * Static instruction class for no-ops. This is a leaf class. 359 */ 360 class Nop : public AlphaStaticInst 361 { 362 /// Disassembly of original instruction. 363 const std::string originalDisassembly; 364 365 public: 366 /// Constructor 367 Nop(const std::string _originalDisassembly, ExtMachInst _machInst) 368 : AlphaStaticInst("nop", _machInst, No_OpClass), 369 originalDisassembly(_originalDisassembly) 370 { 371 flags[IsNop] = true; 372 } 373 374 ~Nop() { } 375 376 std::string 377 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 378 379 %(BasicExecDeclare)s 380 }; 381 382 /// Helper function for decoding nops. Substitute Nop object 383 /// for original inst passed in as arg (and delete latter). 384 static inline 385 AlphaStaticInst * 386 makeNop(AlphaStaticInst *inst) 387 { 388 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); 389 delete inst; 390 return nop; 391 } 392}}; 393 394output decoder {{ 395 std::string Nop::generateDisassembly(Addr pc, 396 const SymbolTable *symtab) const 397 { 398#ifdef SS_COMPATIBLE_DISASSEMBLY 399 return originalDisassembly; 400#else 401 return csprintf("%-10s (%s)", "nop", originalDisassembly); 402#endif 403 } 404}}; 405 406output exec {{ 407 Fault 408 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 409 { 410 return NoFault; 411 } 412}}; 413 414// integer & FP operate instructions use Rc as dest, so check for 415// Rc == 31 to detect nops 416def template OperateNopCheckDecode {{ 417 { 418 AlphaStaticInst *i = new %(class_name)s(machInst); 419 if (RC == 31) { 420 i = makeNop(i); 421 } 422 return i; 423 } 424}}; 425 426// Like BasicOperate format, but generates NOP if RC/FC == 31 427def format BasicOperateWithNopCheck(code, *opt_args) {{ 428 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), 429 opt_args) 430 header_output = BasicDeclare.subst(iop) 431 decoder_output = BasicConstructor.subst(iop) 432 decode_block = OperateNopCheckDecode.subst(iop) 433 exec_output = BasicExecute.subst(iop) 434}}; 435 436// Integer instruction templates, formats, etc. 437##include "int.isa" 438 439// Floating-point instruction templates, formats, etc. 440##include "fp.isa" 441 442// Memory instruction templates, formats, etc. 443##include "mem.isa" 444 445// Branch/jump instruction templates, formats, etc. 446##include "branch.isa" 447 448// PAL instruction templates, formats, etc. 449##include "pal.isa" 450 451// Opcdec fault instruction templates, formats, etc. 452##include "opcdec.isa" 453 454// Unimplemented instruction templates, formats, etc. 455##include "unimp.isa" 456 457// Unknown instruction templates, formats, etc. 458##include "unknown.isa" 459 460// Execution utility functions 461##include "util.isa" 462 463// The actual decoder 464##include "decoder.isa"
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