1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 206 unchanged lines hidden (view full) --- 215 216 /** 217 * Base class for all Alpha static instructions. 218 */ 219 class AlphaStaticInst : public StaticInst 220 { 221 protected: 222 |
223 /// Constructor. 224 AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 225 OpClass __opClass) 226 : StaticInst(mnem, _machInst, __opClass) 227 { 228 } 229 230 /// Print a register name for disassembly given the unique 231 /// dependence tag number (FP or int). |
232 void printReg(std::ostream &os, RegId reg) const; |
233 234 std::string 235 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 236 237 void 238 advancePC(AlphaISA::PCState &pcState) const 239 { 240 pcState.advance(); 241 } 242 }; 243}}; 244 245output decoder {{ 246 void |
247 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const |
248 { |
249 if (reg.regClass == IntRegClass) { 250 ccprintf(os, "r%d", reg.regIdx); |
251 } 252 else { |
253 ccprintf(os, "f%d", reg.regIdx); |
254 } 255 } 256 257 std::string 258 AlphaStaticInst::generateDisassembly(Addr pc, 259 const SymbolTable *symtab) const 260 { 261 std::stringstream ss; --- 209 unchanged lines hidden --- |