59#include "arch/alpha/registers.hh"
60#include "arch/alpha/regredir.hh"
61#include "base/loader/symtab.hh"
62#include "base/cprintf.hh"
63#include "base/fenv.hh"
64#include "config/ss_compatible_fp.hh"
65#include "cpu/thread_context.hh" // for Jump::branchTarget()
66#include "mem/packet.hh"
67#include "sim/full_system.hh"
68
69using namespace AlphaISA;
70}};
71
72output exec {{
73#include <cmath>
74
75#include "arch/alpha/registers.hh"
76#include "arch/alpha/regredir.hh"
77#include "arch/generic/memhelpers.hh"
78#include "base/cp_annotate.hh"
79#include "base/fenv.hh"
80#include "config/ss_compatible_fp.hh"
81#include "cpu/base.hh"
82#include "cpu/exetrace.hh"
83#include "mem/packet.hh"
84#include "mem/packet_access.hh"
85#include "sim/full_system.hh"
86#include "sim/pseudo_inst.hh"
87#include "sim/sim_exit.hh"
88
89using namespace AlphaISA;
90}};
91
92////////////////////////////////////////////////////////////////////
93//
94// Namespace statement. Everything below this line will be in the
95// AlphaISAInst namespace.
96//
97
98
99namespace AlphaISA;
100
101////////////////////////////////////////////////////////////////////
102//
103// Bitfield definitions.
104//
105
106// Universal (format-independent) fields
107def bitfield PALMODE <32:32>;
108def bitfield OPCODE <31:26>;
109def bitfield RA <25:21>;
110def bitfield RB <20:16>;
111
112// Memory format
113def signed bitfield MEMDISP <15: 0>; // displacement
114def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
115
116// Memory-format jumps
117def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
118def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
119
120// Branch format
121def signed bitfield BRDISP <20: 0>; // displacement
122
123// Integer operate format(s>;
124def bitfield INTIMM <20:13>; // integer immediate (literal)
125def bitfield IMM <12:12>; // immediate flag
126def bitfield INTFUNC <11: 5>; // function code
127def bitfield RC < 4: 0>; // dest reg
128
129// Floating-point operate format
130def bitfield FA <25:21>;
131def bitfield FB <20:16>;
132def bitfield FP_FULLFUNC <15: 5>; // complete function code
133 def bitfield FP_TRAPMODE <15:13>; // trapping mode
134 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
135 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
136 def bitfield FP_SRCTYPE <10: 9>; // source reg type
137 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
138 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
139def bitfield FC < 4: 0>; // dest reg
140
141// PALcode format
142def bitfield PALFUNC <25: 0>; // function code
143
144// EV5 PAL instructions:
145// HW_LD/HW_ST
146def bitfield HW_LDST_PHYS <15>; // address is physical
147def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
148def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
149def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
150def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
151def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
152def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
153def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
154
155// HW_REI
156def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
157def bitfield HW_REI_MBZ <13: 0>; // must be zero
158
159// HW_MTPR/MW_MFPR
160def bitfield HW_IPR_IDX <15:0>; // IPR index
161
162// M5 instructions
163def bitfield M5FUNC <7:0>;
164
165def operand_types {{
166 'sb' : 'int8_t',
167 'ub' : 'uint8_t',
168 'sw' : 'int16_t',
169 'uw' : 'uint16_t',
170 'sl' : 'int32_t',
171 'ul' : 'uint32_t',
172 'sq' : 'int64_t',
173 'uq' : 'uint64_t',
174 'sf' : 'float',
175 'df' : 'double'
176}};
177
178def operands {{
179 # Int regs default to unsigned, but code should not count on this.
180 # For clarity, descriptions that depend on unsigned behavior should
181 # explicitly specify '_uq'.
182 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
183 'IsInteger', 1),
184 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
185 'IsInteger', 2),
186 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
187 'IsInteger', 3),
188 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
189 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
190 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
191 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
192 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
193 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
194 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
195 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
196 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
197 # The next two are hacks for non-full-system call-pal emulation
198 'R0': ('IntReg', 'uq', '0', None, 1),
199 'R16': ('IntReg', 'uq', '16', None, 1),
200 'R17': ('IntReg', 'uq', '17', None, 1),
201 'R18': ('IntReg', 'uq', '18', None, 1)
202}};
203
204////////////////////////////////////////////////////////////////////
205//
206// Basic instruction classes/templates/formats etc.
207//
208
209output header {{
210// uncomment the following to get SimpleScalar-compatible disassembly
211// (useful for diffing output traces).
212// #define SS_COMPATIBLE_DISASSEMBLY
213
214 /**
215 * Base class for all Alpha static instructions.
216 */
217 class AlphaStaticInst : public StaticInst
218 {
219 protected:
220
221 /// Make AlphaISA register dependence tags directly visible in
222 /// this class and derived classes. Maybe these should really
223 /// live here and not in the AlphaISA namespace.
224 enum DependenceTags {
225 FP_Base_DepTag = AlphaISA::FP_Base_DepTag
226 };
227
228 /// Constructor.
229 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
230 OpClass __opClass)
231 : StaticInst(mnem, _machInst, __opClass)
232 {
233 }
234
235 /// Print a register name for disassembly given the unique
236 /// dependence tag number (FP or int).
237 void printReg(std::ostream &os, int reg) const;
238
239 std::string
240 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
241
242 void
243 advancePC(AlphaISA::PCState &pcState) const
244 {
245 pcState.advance();
246 }
247 };
248}};
249
250output decoder {{
251 void
252 AlphaStaticInst::printReg(std::ostream &os, int reg) const
253 {
254 if (reg < FP_Base_DepTag) {
255 ccprintf(os, "r%d", reg);
256 }
257 else {
258 ccprintf(os, "f%d", reg - FP_Base_DepTag);
259 }
260 }
261
262 std::string
263 AlphaStaticInst::generateDisassembly(Addr pc,
264 const SymbolTable *symtab) const
265 {
266 std::stringstream ss;
267
268 ccprintf(ss, "%-10s ", mnemonic);
269
270 // just print the first two source regs... if there's
271 // a third one, it's a read-modify-write dest (Rc),
272 // e.g. for CMOVxx
273 if (_numSrcRegs > 0) {
274 printReg(ss, _srcRegIdx[0]);
275 }
276 if (_numSrcRegs > 1) {
277 ss << ",";
278 printReg(ss, _srcRegIdx[1]);
279 }
280
281 // just print the first dest... if there's a second one,
282 // it's generally implicit
283 if (_numDestRegs > 0) {
284 if (_numSrcRegs > 0)
285 ss << ",";
286 printReg(ss, _destRegIdx[0]);
287 }
288
289 return ss.str();
290 }
291}};
292
293// Declarations for execute() methods.
294def template BasicExecDeclare {{
295 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
296}};
297
298// Basic instruction class declaration template.
299def template BasicDeclare {{
300 /**
301 * Static instruction class for "%(mnemonic)s".
302 */
303 class %(class_name)s : public %(base_class)s
304 {
305 public:
306 /// Constructor.
307 %(class_name)s(ExtMachInst machInst);
308
309 %(BasicExecDeclare)s
310 };
311}};
312
313// Basic instruction class constructor template.
314def template BasicConstructor {{
315 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
317 {
318 %(constructor)s;
319 }
320}};
321
322// Basic instruction class execute method template.
323def template BasicExecute {{
324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
325 Trace::InstRecord *traceData) const
326 {
327 Fault fault = NoFault;
328
329 %(fp_enable_check)s;
330 %(op_decl)s;
331 %(op_rd)s;
332 %(code)s;
333
334 if (fault == NoFault) {
335 %(op_wb)s;
336 }
337
338 return fault;
339 }
340}};
341
342// Basic decode template.
343def template BasicDecode {{
344 return new %(class_name)s(machInst);
345}};
346
347// Basic decode template, passing mnemonic in as string arg to constructor.
348def template BasicDecodeWithMnemonic {{
349 return new %(class_name)s("%(mnemonic)s", machInst);
350}};
351
352// The most basic instruction format... used only for a few misc. insts
353def format BasicOperate(code, *flags) {{
354 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
355 header_output = BasicDeclare.subst(iop)
356 decoder_output = BasicConstructor.subst(iop)
357 decode_block = BasicDecode.subst(iop)
358 exec_output = BasicExecute.subst(iop)
359}};
360
361
362
363////////////////////////////////////////////////////////////////////
364//
365// Nop
366//
367
368output header {{
369 /**
370 * Static instruction class for no-ops. This is a leaf class.
371 */
372 class Nop : public AlphaStaticInst
373 {
374 /// Disassembly of original instruction.
375 const std::string originalDisassembly;
376
377 public:
378 /// Constructor
379 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
380 : AlphaStaticInst("nop", _machInst, No_OpClass),
381 originalDisassembly(_originalDisassembly)
382 {
383 flags[IsNop] = true;
384 }
385
386 ~Nop() { }
387
388 std::string
389 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
390
391 %(BasicExecDeclare)s
392 };
393
394 /// Helper function for decoding nops. Substitute Nop object
395 /// for original inst passed in as arg (and delete latter).
396 static inline
397 AlphaStaticInst *
398 makeNop(AlphaStaticInst *inst)
399 {
400 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
401 delete inst;
402 return nop;
403 }
404}};
405
406output decoder {{
407 std::string Nop::generateDisassembly(Addr pc,
408 const SymbolTable *symtab) const
409 {
410#ifdef SS_COMPATIBLE_DISASSEMBLY
411 return originalDisassembly;
412#else
413 return csprintf("%-10s (%s)", "nop", originalDisassembly);
414#endif
415 }
416}};
417
418output exec {{
419 Fault
420 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
421 {
422 return NoFault;
423 }
424}};
425
426// integer & FP operate instructions use Rc as dest, so check for
427// Rc == 31 to detect nops
428def template OperateNopCheckDecode {{
429 {
430 AlphaStaticInst *i = new %(class_name)s(machInst);
431 if (RC == 31) {
432 i = makeNop(i);
433 }
434 return i;
435 }
436}};
437
438// Like BasicOperate format, but generates NOP if RC/FC == 31
439def format BasicOperateWithNopCheck(code, *opt_args) {{
440 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
441 header_output = BasicDeclare.subst(iop)
442 decoder_output = BasicConstructor.subst(iop)
443 decode_block = OperateNopCheckDecode.subst(iop)
444 exec_output = BasicExecute.subst(iop)
445}};
446
447// Integer instruction templates, formats, etc.
448##include "int.isa"
449
450// Floating-point instruction templates, formats, etc.
451##include "fp.isa"
452
453// Memory instruction templates, formats, etc.
454##include "mem.isa"
455
456// Branch/jump instruction templates, formats, etc.
457##include "branch.isa"
458
459// PAL instruction templates, formats, etc.
460##include "pal.isa"
461
462// Opcdec fault instruction templates, formats, etc.
463##include "opcdec.isa"
464
465// Unimplemented instruction templates, formats, etc.
466##include "unimp.isa"
467
468// Unknown instruction templates, formats, etc.
469##include "unknown.isa"
470
471// Execution utility functions
472##include "util.isa"
473
474// The actual decoder
475##include "decoder.isa"
| 60#include "arch/alpha/registers.hh"
61#include "arch/alpha/regredir.hh"
62#include "base/loader/symtab.hh"
63#include "base/cprintf.hh"
64#include "base/fenv.hh"
65#include "config/ss_compatible_fp.hh"
66#include "cpu/thread_context.hh" // for Jump::branchTarget()
67#include "mem/packet.hh"
68#include "sim/full_system.hh"
69
70using namespace AlphaISA;
71}};
72
73output exec {{
74#include <cmath>
75
76#include "arch/alpha/registers.hh"
77#include "arch/alpha/regredir.hh"
78#include "arch/generic/memhelpers.hh"
79#include "base/cp_annotate.hh"
80#include "base/fenv.hh"
81#include "config/ss_compatible_fp.hh"
82#include "cpu/base.hh"
83#include "cpu/exetrace.hh"
84#include "mem/packet.hh"
85#include "mem/packet_access.hh"
86#include "sim/full_system.hh"
87#include "sim/pseudo_inst.hh"
88#include "sim/sim_exit.hh"
89
90using namespace AlphaISA;
91}};
92
93////////////////////////////////////////////////////////////////////
94//
95// Namespace statement. Everything below this line will be in the
96// AlphaISAInst namespace.
97//
98
99
100namespace AlphaISA;
101
102////////////////////////////////////////////////////////////////////
103//
104// Bitfield definitions.
105//
106
107// Universal (format-independent) fields
108def bitfield PALMODE <32:32>;
109def bitfield OPCODE <31:26>;
110def bitfield RA <25:21>;
111def bitfield RB <20:16>;
112
113// Memory format
114def signed bitfield MEMDISP <15: 0>; // displacement
115def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
116
117// Memory-format jumps
118def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
119def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
120
121// Branch format
122def signed bitfield BRDISP <20: 0>; // displacement
123
124// Integer operate format(s>;
125def bitfield INTIMM <20:13>; // integer immediate (literal)
126def bitfield IMM <12:12>; // immediate flag
127def bitfield INTFUNC <11: 5>; // function code
128def bitfield RC < 4: 0>; // dest reg
129
130// Floating-point operate format
131def bitfield FA <25:21>;
132def bitfield FB <20:16>;
133def bitfield FP_FULLFUNC <15: 5>; // complete function code
134 def bitfield FP_TRAPMODE <15:13>; // trapping mode
135 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
136 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
137 def bitfield FP_SRCTYPE <10: 9>; // source reg type
138 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
139 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
140def bitfield FC < 4: 0>; // dest reg
141
142// PALcode format
143def bitfield PALFUNC <25: 0>; // function code
144
145// EV5 PAL instructions:
146// HW_LD/HW_ST
147def bitfield HW_LDST_PHYS <15>; // address is physical
148def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
149def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
150def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
151def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
152def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
153def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
154def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
155
156// HW_REI
157def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
158def bitfield HW_REI_MBZ <13: 0>; // must be zero
159
160// HW_MTPR/MW_MFPR
161def bitfield HW_IPR_IDX <15:0>; // IPR index
162
163// M5 instructions
164def bitfield M5FUNC <7:0>;
165
166def operand_types {{
167 'sb' : 'int8_t',
168 'ub' : 'uint8_t',
169 'sw' : 'int16_t',
170 'uw' : 'uint16_t',
171 'sl' : 'int32_t',
172 'ul' : 'uint32_t',
173 'sq' : 'int64_t',
174 'uq' : 'uint64_t',
175 'sf' : 'float',
176 'df' : 'double'
177}};
178
179def operands {{
180 # Int regs default to unsigned, but code should not count on this.
181 # For clarity, descriptions that depend on unsigned behavior should
182 # explicitly specify '_uq'.
183 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
184 'IsInteger', 1),
185 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
186 'IsInteger', 2),
187 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
188 'IsInteger', 3),
189 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
190 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
191 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
192 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
193 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
194 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
195 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
196 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
197 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
198 # The next two are hacks for non-full-system call-pal emulation
199 'R0': ('IntReg', 'uq', '0', None, 1),
200 'R16': ('IntReg', 'uq', '16', None, 1),
201 'R17': ('IntReg', 'uq', '17', None, 1),
202 'R18': ('IntReg', 'uq', '18', None, 1)
203}};
204
205////////////////////////////////////////////////////////////////////
206//
207// Basic instruction classes/templates/formats etc.
208//
209
210output header {{
211// uncomment the following to get SimpleScalar-compatible disassembly
212// (useful for diffing output traces).
213// #define SS_COMPATIBLE_DISASSEMBLY
214
215 /**
216 * Base class for all Alpha static instructions.
217 */
218 class AlphaStaticInst : public StaticInst
219 {
220 protected:
221
222 /// Make AlphaISA register dependence tags directly visible in
223 /// this class and derived classes. Maybe these should really
224 /// live here and not in the AlphaISA namespace.
225 enum DependenceTags {
226 FP_Base_DepTag = AlphaISA::FP_Base_DepTag
227 };
228
229 /// Constructor.
230 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
231 OpClass __opClass)
232 : StaticInst(mnem, _machInst, __opClass)
233 {
234 }
235
236 /// Print a register name for disassembly given the unique
237 /// dependence tag number (FP or int).
238 void printReg(std::ostream &os, int reg) const;
239
240 std::string
241 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
242
243 void
244 advancePC(AlphaISA::PCState &pcState) const
245 {
246 pcState.advance();
247 }
248 };
249}};
250
251output decoder {{
252 void
253 AlphaStaticInst::printReg(std::ostream &os, int reg) const
254 {
255 if (reg < FP_Base_DepTag) {
256 ccprintf(os, "r%d", reg);
257 }
258 else {
259 ccprintf(os, "f%d", reg - FP_Base_DepTag);
260 }
261 }
262
263 std::string
264 AlphaStaticInst::generateDisassembly(Addr pc,
265 const SymbolTable *symtab) const
266 {
267 std::stringstream ss;
268
269 ccprintf(ss, "%-10s ", mnemonic);
270
271 // just print the first two source regs... if there's
272 // a third one, it's a read-modify-write dest (Rc),
273 // e.g. for CMOVxx
274 if (_numSrcRegs > 0) {
275 printReg(ss, _srcRegIdx[0]);
276 }
277 if (_numSrcRegs > 1) {
278 ss << ",";
279 printReg(ss, _srcRegIdx[1]);
280 }
281
282 // just print the first dest... if there's a second one,
283 // it's generally implicit
284 if (_numDestRegs > 0) {
285 if (_numSrcRegs > 0)
286 ss << ",";
287 printReg(ss, _destRegIdx[0]);
288 }
289
290 return ss.str();
291 }
292}};
293
294// Declarations for execute() methods.
295def template BasicExecDeclare {{
296 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
297}};
298
299// Basic instruction class declaration template.
300def template BasicDeclare {{
301 /**
302 * Static instruction class for "%(mnemonic)s".
303 */
304 class %(class_name)s : public %(base_class)s
305 {
306 public:
307 /// Constructor.
308 %(class_name)s(ExtMachInst machInst);
309
310 %(BasicExecDeclare)s
311 };
312}};
313
314// Basic instruction class constructor template.
315def template BasicConstructor {{
316 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
317 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
318 {
319 %(constructor)s;
320 }
321}};
322
323// Basic instruction class execute method template.
324def template BasicExecute {{
325 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
326 Trace::InstRecord *traceData) const
327 {
328 Fault fault = NoFault;
329
330 %(fp_enable_check)s;
331 %(op_decl)s;
332 %(op_rd)s;
333 %(code)s;
334
335 if (fault == NoFault) {
336 %(op_wb)s;
337 }
338
339 return fault;
340 }
341}};
342
343// Basic decode template.
344def template BasicDecode {{
345 return new %(class_name)s(machInst);
346}};
347
348// Basic decode template, passing mnemonic in as string arg to constructor.
349def template BasicDecodeWithMnemonic {{
350 return new %(class_name)s("%(mnemonic)s", machInst);
351}};
352
353// The most basic instruction format... used only for a few misc. insts
354def format BasicOperate(code, *flags) {{
355 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
356 header_output = BasicDeclare.subst(iop)
357 decoder_output = BasicConstructor.subst(iop)
358 decode_block = BasicDecode.subst(iop)
359 exec_output = BasicExecute.subst(iop)
360}};
361
362
363
364////////////////////////////////////////////////////////////////////
365//
366// Nop
367//
368
369output header {{
370 /**
371 * Static instruction class for no-ops. This is a leaf class.
372 */
373 class Nop : public AlphaStaticInst
374 {
375 /// Disassembly of original instruction.
376 const std::string originalDisassembly;
377
378 public:
379 /// Constructor
380 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
381 : AlphaStaticInst("nop", _machInst, No_OpClass),
382 originalDisassembly(_originalDisassembly)
383 {
384 flags[IsNop] = true;
385 }
386
387 ~Nop() { }
388
389 std::string
390 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
391
392 %(BasicExecDeclare)s
393 };
394
395 /// Helper function for decoding nops. Substitute Nop object
396 /// for original inst passed in as arg (and delete latter).
397 static inline
398 AlphaStaticInst *
399 makeNop(AlphaStaticInst *inst)
400 {
401 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
402 delete inst;
403 return nop;
404 }
405}};
406
407output decoder {{
408 std::string Nop::generateDisassembly(Addr pc,
409 const SymbolTable *symtab) const
410 {
411#ifdef SS_COMPATIBLE_DISASSEMBLY
412 return originalDisassembly;
413#else
414 return csprintf("%-10s (%s)", "nop", originalDisassembly);
415#endif
416 }
417}};
418
419output exec {{
420 Fault
421 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
422 {
423 return NoFault;
424 }
425}};
426
427// integer & FP operate instructions use Rc as dest, so check for
428// Rc == 31 to detect nops
429def template OperateNopCheckDecode {{
430 {
431 AlphaStaticInst *i = new %(class_name)s(machInst);
432 if (RC == 31) {
433 i = makeNop(i);
434 }
435 return i;
436 }
437}};
438
439// Like BasicOperate format, but generates NOP if RC/FC == 31
440def format BasicOperateWithNopCheck(code, *opt_args) {{
441 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
442 header_output = BasicDeclare.subst(iop)
443 decoder_output = BasicConstructor.subst(iop)
444 decode_block = OperateNopCheckDecode.subst(iop)
445 exec_output = BasicExecute.subst(iop)
446}};
447
448// Integer instruction templates, formats, etc.
449##include "int.isa"
450
451// Floating-point instruction templates, formats, etc.
452##include "fp.isa"
453
454// Memory instruction templates, formats, etc.
455##include "mem.isa"
456
457// Branch/jump instruction templates, formats, etc.
458##include "branch.isa"
459
460// PAL instruction templates, formats, etc.
461##include "pal.isa"
462
463// Opcdec fault instruction templates, formats, etc.
464##include "opcdec.isa"
465
466// Unimplemented instruction templates, formats, etc.
467##include "unimp.isa"
468
469// Unknown instruction templates, formats, etc.
470##include "unknown.isa"
471
472// Execution utility functions
473##include "util.isa"
474
475// The actual decoder
476##include "decoder.isa"
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