84#include "sim/pseudo_inst.hh"
85#include "sim/sim_exit.hh"
86
87using namespace AlphaISA;
88}};
89
90////////////////////////////////////////////////////////////////////
91//
92// Namespace statement. Everything below this line will be in the
93// AlphaISAInst namespace.
94//
95
96
97namespace AlphaISA;
98
99////////////////////////////////////////////////////////////////////
100//
101// Bitfield definitions.
102//
103
104// Universal (format-independent) fields
105def bitfield PALMODE <32:32>;
106def bitfield OPCODE <31:26>;
107def bitfield RA <25:21>;
108def bitfield RB <20:16>;
109
110// Memory format
111def signed bitfield MEMDISP <15: 0>; // displacement
112def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
113
114// Memory-format jumps
115def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
116def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
117
118// Branch format
119def signed bitfield BRDISP <20: 0>; // displacement
120
121// Integer operate format(s>;
122def bitfield INTIMM <20:13>; // integer immediate (literal)
123def bitfield IMM <12:12>; // immediate flag
124def bitfield INTFUNC <11: 5>; // function code
125def bitfield RC < 4: 0>; // dest reg
126
127// Floating-point operate format
128def bitfield FA <25:21>;
129def bitfield FB <20:16>;
130def bitfield FP_FULLFUNC <15: 5>; // complete function code
131 def bitfield FP_TRAPMODE <15:13>; // trapping mode
132 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
133 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
134 def bitfield FP_SRCTYPE <10: 9>; // source reg type
135 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
136 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
137def bitfield FC < 4: 0>; // dest reg
138
139// PALcode format
140def bitfield PALFUNC <25: 0>; // function code
141
142// EV5 PAL instructions:
143// HW_LD/HW_ST
144def bitfield HW_LDST_PHYS <15>; // address is physical
145def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
146def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
147def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
148def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
149def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
150def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
151def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
152
153// HW_REI
154def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
155def bitfield HW_REI_MBZ <13: 0>; // must be zero
156
157// HW_MTPR/MW_MFPR
158def bitfield HW_IPR_IDX <15:0>; // IPR index
159
160// M5 instructions
161def bitfield M5FUNC <7:0>;
162
163def operand_types {{
164 'sb' : 'int8_t',
165 'ub' : 'uint8_t',
166 'sw' : 'int16_t',
167 'uw' : 'uint16_t',
168 'sl' : 'int32_t',
169 'ul' : 'uint32_t',
170 'sq' : 'int64_t',
171 'uq' : 'uint64_t',
172 'sf' : 'float',
173 'df' : 'double'
174}};
175
176def operands {{
177 # Int regs default to unsigned, but code should not count on this.
178 # For clarity, descriptions that depend on unsigned behavior should
179 # explicitly specify '_uq'.
180 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
181 'IsInteger', 1),
182 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
183 'IsInteger', 2),
184 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
185 'IsInteger', 3),
186 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
187 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
188 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
189 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
190 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
191 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
192 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
193 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
194 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
195 # The next two are hacks for non-full-system call-pal emulation
196 'R0': ('IntReg', 'uq', '0', None, 1),
197 'R16': ('IntReg', 'uq', '16', None, 1),
198 'R17': ('IntReg', 'uq', '17', None, 1),
199 'R18': ('IntReg', 'uq', '18', None, 1)
200}};
201
202////////////////////////////////////////////////////////////////////
203//
204// Basic instruction classes/templates/formats etc.
205//
206
207output header {{
208// uncomment the following to get SimpleScalar-compatible disassembly
209// (useful for diffing output traces).
210// #define SS_COMPATIBLE_DISASSEMBLY
211
212 /**
213 * Base class for all Alpha static instructions.
214 */
215 class AlphaStaticInst : public StaticInst
216 {
217 protected:
218
219 /// Make AlphaISA register dependence tags directly visible in
220 /// this class and derived classes. Maybe these should really
221 /// live here and not in the AlphaISA namespace.
222 enum DependenceTags {
223 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
224 };
225
226 /// Constructor.
227 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
228 OpClass __opClass)
229 : StaticInst(mnem, _machInst, __opClass)
230 {
231 }
232
233 /// Print a register name for disassembly given the unique
234 /// dependence tag number (FP or int).
235 void printReg(std::ostream &os, int reg) const;
236
237 std::string
238 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
239
240 void
241 advancePC(AlphaISA::PCState &pcState) const
242 {
243 pcState.advance();
244 }
245 };
246}};
247
248output decoder {{
249 void
250 AlphaStaticInst::printReg(std::ostream &os, int reg) const
251 {
252 if (reg < FP_Base_DepTag) {
253 ccprintf(os, "r%d", reg);
254 }
255 else {
256 ccprintf(os, "f%d", reg - FP_Base_DepTag);
257 }
258 }
259
260 std::string
261 AlphaStaticInst::generateDisassembly(Addr pc,
262 const SymbolTable *symtab) const
263 {
264 std::stringstream ss;
265
266 ccprintf(ss, "%-10s ", mnemonic);
267
268 // just print the first two source regs... if there's
269 // a third one, it's a read-modify-write dest (Rc),
270 // e.g. for CMOVxx
271 if (_numSrcRegs > 0) {
272 printReg(ss, _srcRegIdx[0]);
273 }
274 if (_numSrcRegs > 1) {
275 ss << ",";
276 printReg(ss, _srcRegIdx[1]);
277 }
278
279 // just print the first dest... if there's a second one,
280 // it's generally implicit
281 if (_numDestRegs > 0) {
282 if (_numSrcRegs > 0)
283 ss << ",";
284 printReg(ss, _destRegIdx[0]);
285 }
286
287 return ss.str();
288 }
289}};
290
291// Declarations for execute() methods.
292def template BasicExecDeclare {{
293 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
294}};
295
296// Basic instruction class declaration template.
297def template BasicDeclare {{
298 /**
299 * Static instruction class for "%(mnemonic)s".
300 */
301 class %(class_name)s : public %(base_class)s
302 {
303 public:
304 /// Constructor.
305 %(class_name)s(ExtMachInst machInst);
306
307 %(BasicExecDeclare)s
308 };
309}};
310
311// Basic instruction class constructor template.
312def template BasicConstructor {{
313 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
314 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
315 {
316 %(constructor)s;
317 }
318}};
319
320// Basic instruction class execute method template.
321def template BasicExecute {{
322 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
323 Trace::InstRecord *traceData) const
324 {
325 Fault fault = NoFault;
326
327 %(fp_enable_check)s;
328 %(op_decl)s;
329 %(op_rd)s;
330 %(code)s;
331
332 if (fault == NoFault) {
333 %(op_wb)s;
334 }
335
336 return fault;
337 }
338}};
339
340// Basic decode template.
341def template BasicDecode {{
342 return new %(class_name)s(machInst);
343}};
344
345// Basic decode template, passing mnemonic in as string arg to constructor.
346def template BasicDecodeWithMnemonic {{
347 return new %(class_name)s("%(mnemonic)s", machInst);
348}};
349
350// The most basic instruction format... used only for a few misc. insts
351def format BasicOperate(code, *flags) {{
352 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
353 header_output = BasicDeclare.subst(iop)
354 decoder_output = BasicConstructor.subst(iop)
355 decode_block = BasicDecode.subst(iop)
356 exec_output = BasicExecute.subst(iop)
357}};
358
359
360
361////////////////////////////////////////////////////////////////////
362//
363// Nop
364//
365
366output header {{
367 /**
368 * Static instruction class for no-ops. This is a leaf class.
369 */
370 class Nop : public AlphaStaticInst
371 {
372 /// Disassembly of original instruction.
373 const std::string originalDisassembly;
374
375 public:
376 /// Constructor
377 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
378 : AlphaStaticInst("nop", _machInst, No_OpClass),
379 originalDisassembly(_originalDisassembly)
380 {
381 flags[IsNop] = true;
382 }
383
384 ~Nop() { }
385
386 std::string
387 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
388
389 %(BasicExecDeclare)s
390 };
391
392 /// Helper function for decoding nops. Substitute Nop object
393 /// for original inst passed in as arg (and delete latter).
394 static inline
395 AlphaStaticInst *
396 makeNop(AlphaStaticInst *inst)
397 {
398 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
399 delete inst;
400 return nop;
401 }
402}};
403
404output decoder {{
405 std::string Nop::generateDisassembly(Addr pc,
406 const SymbolTable *symtab) const
407 {
408#ifdef SS_COMPATIBLE_DISASSEMBLY
409 return originalDisassembly;
410#else
411 return csprintf("%-10s (%s)", "nop", originalDisassembly);
412#endif
413 }
414}};
415
416output exec {{
417 Fault
418 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
419 {
420 return NoFault;
421 }
422}};
423
424// integer & FP operate instructions use Rc as dest, so check for
425// Rc == 31 to detect nops
426def template OperateNopCheckDecode {{
427 {
428 AlphaStaticInst *i = new %(class_name)s(machInst);
429 if (RC == 31) {
430 i = makeNop(i);
431 }
432 return i;
433 }
434}};
435
436// Like BasicOperate format, but generates NOP if RC/FC == 31
437def format BasicOperateWithNopCheck(code, *opt_args) {{
438 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
439 header_output = BasicDeclare.subst(iop)
440 decoder_output = BasicConstructor.subst(iop)
441 decode_block = OperateNopCheckDecode.subst(iop)
442 exec_output = BasicExecute.subst(iop)
443}};
444
445// Integer instruction templates, formats, etc.
446##include "int.isa"
447
448// Floating-point instruction templates, formats, etc.
449##include "fp.isa"
450
451// Memory instruction templates, formats, etc.
452##include "mem.isa"
453
454// Branch/jump instruction templates, formats, etc.
455##include "branch.isa"
456
457// PAL instruction templates, formats, etc.
458##include "pal.isa"
459
460// Opcdec fault instruction templates, formats, etc.
461##include "opcdec.isa"
462
463// Unimplemented instruction templates, formats, etc.
464##include "unimp.isa"
465
466// Unknown instruction templates, formats, etc.
467##include "unknown.isa"
468
469// Execution utility functions
470##include "util.isa"
471
472// The actual decoder
473##include "decoder.isa"
| 86#include "sim/pseudo_inst.hh"
87#include "sim/sim_exit.hh"
88
89using namespace AlphaISA;
90}};
91
92////////////////////////////////////////////////////////////////////
93//
94// Namespace statement. Everything below this line will be in the
95// AlphaISAInst namespace.
96//
97
98
99namespace AlphaISA;
100
101////////////////////////////////////////////////////////////////////
102//
103// Bitfield definitions.
104//
105
106// Universal (format-independent) fields
107def bitfield PALMODE <32:32>;
108def bitfield OPCODE <31:26>;
109def bitfield RA <25:21>;
110def bitfield RB <20:16>;
111
112// Memory format
113def signed bitfield MEMDISP <15: 0>; // displacement
114def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
115
116// Memory-format jumps
117def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
118def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
119
120// Branch format
121def signed bitfield BRDISP <20: 0>; // displacement
122
123// Integer operate format(s>;
124def bitfield INTIMM <20:13>; // integer immediate (literal)
125def bitfield IMM <12:12>; // immediate flag
126def bitfield INTFUNC <11: 5>; // function code
127def bitfield RC < 4: 0>; // dest reg
128
129// Floating-point operate format
130def bitfield FA <25:21>;
131def bitfield FB <20:16>;
132def bitfield FP_FULLFUNC <15: 5>; // complete function code
133 def bitfield FP_TRAPMODE <15:13>; // trapping mode
134 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
135 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
136 def bitfield FP_SRCTYPE <10: 9>; // source reg type
137 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
138 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
139def bitfield FC < 4: 0>; // dest reg
140
141// PALcode format
142def bitfield PALFUNC <25: 0>; // function code
143
144// EV5 PAL instructions:
145// HW_LD/HW_ST
146def bitfield HW_LDST_PHYS <15>; // address is physical
147def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
148def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
149def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
150def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
151def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
152def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
153def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
154
155// HW_REI
156def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
157def bitfield HW_REI_MBZ <13: 0>; // must be zero
158
159// HW_MTPR/MW_MFPR
160def bitfield HW_IPR_IDX <15:0>; // IPR index
161
162// M5 instructions
163def bitfield M5FUNC <7:0>;
164
165def operand_types {{
166 'sb' : 'int8_t',
167 'ub' : 'uint8_t',
168 'sw' : 'int16_t',
169 'uw' : 'uint16_t',
170 'sl' : 'int32_t',
171 'ul' : 'uint32_t',
172 'sq' : 'int64_t',
173 'uq' : 'uint64_t',
174 'sf' : 'float',
175 'df' : 'double'
176}};
177
178def operands {{
179 # Int regs default to unsigned, but code should not count on this.
180 # For clarity, descriptions that depend on unsigned behavior should
181 # explicitly specify '_uq'.
182 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
183 'IsInteger', 1),
184 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
185 'IsInteger', 2),
186 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
187 'IsInteger', 3),
188 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
189 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
190 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
191 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
192 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
193 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
194 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
195 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
196 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
197 # The next two are hacks for non-full-system call-pal emulation
198 'R0': ('IntReg', 'uq', '0', None, 1),
199 'R16': ('IntReg', 'uq', '16', None, 1),
200 'R17': ('IntReg', 'uq', '17', None, 1),
201 'R18': ('IntReg', 'uq', '18', None, 1)
202}};
203
204////////////////////////////////////////////////////////////////////
205//
206// Basic instruction classes/templates/formats etc.
207//
208
209output header {{
210// uncomment the following to get SimpleScalar-compatible disassembly
211// (useful for diffing output traces).
212// #define SS_COMPATIBLE_DISASSEMBLY
213
214 /**
215 * Base class for all Alpha static instructions.
216 */
217 class AlphaStaticInst : public StaticInst
218 {
219 protected:
220
221 /// Make AlphaISA register dependence tags directly visible in
222 /// this class and derived classes. Maybe these should really
223 /// live here and not in the AlphaISA namespace.
224 enum DependenceTags {
225 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
226 };
227
228 /// Constructor.
229 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
230 OpClass __opClass)
231 : StaticInst(mnem, _machInst, __opClass)
232 {
233 }
234
235 /// Print a register name for disassembly given the unique
236 /// dependence tag number (FP or int).
237 void printReg(std::ostream &os, int reg) const;
238
239 std::string
240 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
241
242 void
243 advancePC(AlphaISA::PCState &pcState) const
244 {
245 pcState.advance();
246 }
247 };
248}};
249
250output decoder {{
251 void
252 AlphaStaticInst::printReg(std::ostream &os, int reg) const
253 {
254 if (reg < FP_Base_DepTag) {
255 ccprintf(os, "r%d", reg);
256 }
257 else {
258 ccprintf(os, "f%d", reg - FP_Base_DepTag);
259 }
260 }
261
262 std::string
263 AlphaStaticInst::generateDisassembly(Addr pc,
264 const SymbolTable *symtab) const
265 {
266 std::stringstream ss;
267
268 ccprintf(ss, "%-10s ", mnemonic);
269
270 // just print the first two source regs... if there's
271 // a third one, it's a read-modify-write dest (Rc),
272 // e.g. for CMOVxx
273 if (_numSrcRegs > 0) {
274 printReg(ss, _srcRegIdx[0]);
275 }
276 if (_numSrcRegs > 1) {
277 ss << ",";
278 printReg(ss, _srcRegIdx[1]);
279 }
280
281 // just print the first dest... if there's a second one,
282 // it's generally implicit
283 if (_numDestRegs > 0) {
284 if (_numSrcRegs > 0)
285 ss << ",";
286 printReg(ss, _destRegIdx[0]);
287 }
288
289 return ss.str();
290 }
291}};
292
293// Declarations for execute() methods.
294def template BasicExecDeclare {{
295 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
296}};
297
298// Basic instruction class declaration template.
299def template BasicDeclare {{
300 /**
301 * Static instruction class for "%(mnemonic)s".
302 */
303 class %(class_name)s : public %(base_class)s
304 {
305 public:
306 /// Constructor.
307 %(class_name)s(ExtMachInst machInst);
308
309 %(BasicExecDeclare)s
310 };
311}};
312
313// Basic instruction class constructor template.
314def template BasicConstructor {{
315 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
317 {
318 %(constructor)s;
319 }
320}};
321
322// Basic instruction class execute method template.
323def template BasicExecute {{
324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
325 Trace::InstRecord *traceData) const
326 {
327 Fault fault = NoFault;
328
329 %(fp_enable_check)s;
330 %(op_decl)s;
331 %(op_rd)s;
332 %(code)s;
333
334 if (fault == NoFault) {
335 %(op_wb)s;
336 }
337
338 return fault;
339 }
340}};
341
342// Basic decode template.
343def template BasicDecode {{
344 return new %(class_name)s(machInst);
345}};
346
347// Basic decode template, passing mnemonic in as string arg to constructor.
348def template BasicDecodeWithMnemonic {{
349 return new %(class_name)s("%(mnemonic)s", machInst);
350}};
351
352// The most basic instruction format... used only for a few misc. insts
353def format BasicOperate(code, *flags) {{
354 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
355 header_output = BasicDeclare.subst(iop)
356 decoder_output = BasicConstructor.subst(iop)
357 decode_block = BasicDecode.subst(iop)
358 exec_output = BasicExecute.subst(iop)
359}};
360
361
362
363////////////////////////////////////////////////////////////////////
364//
365// Nop
366//
367
368output header {{
369 /**
370 * Static instruction class for no-ops. This is a leaf class.
371 */
372 class Nop : public AlphaStaticInst
373 {
374 /// Disassembly of original instruction.
375 const std::string originalDisassembly;
376
377 public:
378 /// Constructor
379 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
380 : AlphaStaticInst("nop", _machInst, No_OpClass),
381 originalDisassembly(_originalDisassembly)
382 {
383 flags[IsNop] = true;
384 }
385
386 ~Nop() { }
387
388 std::string
389 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
390
391 %(BasicExecDeclare)s
392 };
393
394 /// Helper function for decoding nops. Substitute Nop object
395 /// for original inst passed in as arg (and delete latter).
396 static inline
397 AlphaStaticInst *
398 makeNop(AlphaStaticInst *inst)
399 {
400 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
401 delete inst;
402 return nop;
403 }
404}};
405
406output decoder {{
407 std::string Nop::generateDisassembly(Addr pc,
408 const SymbolTable *symtab) const
409 {
410#ifdef SS_COMPATIBLE_DISASSEMBLY
411 return originalDisassembly;
412#else
413 return csprintf("%-10s (%s)", "nop", originalDisassembly);
414#endif
415 }
416}};
417
418output exec {{
419 Fault
420 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
421 {
422 return NoFault;
423 }
424}};
425
426// integer & FP operate instructions use Rc as dest, so check for
427// Rc == 31 to detect nops
428def template OperateNopCheckDecode {{
429 {
430 AlphaStaticInst *i = new %(class_name)s(machInst);
431 if (RC == 31) {
432 i = makeNop(i);
433 }
434 return i;
435 }
436}};
437
438// Like BasicOperate format, but generates NOP if RC/FC == 31
439def format BasicOperateWithNopCheck(code, *opt_args) {{
440 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
441 header_output = BasicDeclare.subst(iop)
442 decoder_output = BasicConstructor.subst(iop)
443 decode_block = OperateNopCheckDecode.subst(iop)
444 exec_output = BasicExecute.subst(iop)
445}};
446
447// Integer instruction templates, formats, etc.
448##include "int.isa"
449
450// Floating-point instruction templates, formats, etc.
451##include "fp.isa"
452
453// Memory instruction templates, formats, etc.
454##include "mem.isa"
455
456// Branch/jump instruction templates, formats, etc.
457##include "branch.isa"
458
459// PAL instruction templates, formats, etc.
460##include "pal.isa"
461
462// Opcdec fault instruction templates, formats, etc.
463##include "opcdec.isa"
464
465// Unimplemented instruction templates, formats, etc.
466##include "unimp.isa"
467
468// Unknown instruction templates, formats, etc.
469##include "unknown.isa"
470
471// Execution utility functions
472##include "util.isa"
473
474// The actual decoder
475##include "decoder.isa"
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