74#include "base/fenv.hh"
75#include "config/ss_compatible_fp.hh"
76#include "cpu/base.hh"
77#include "cpu/exetrace.hh"
78#include "mem/packet.hh"
79#include "mem/packet_access.hh"
80#include "sim/sim_exit.hh"
81
82using namespace AlphaISA;
83}};
84
85////////////////////////////////////////////////////////////////////
86//
87// Namespace statement. Everything below this line will be in the
88// AlphaISAInst namespace.
89//
90
91
92namespace AlphaISA;
93
94////////////////////////////////////////////////////////////////////
95//
96// Bitfield definitions.
97//
98
99// Universal (format-independent) fields
100def bitfield PALMODE <32:32>;
101def bitfield OPCODE <31:26>;
102def bitfield RA <25:21>;
103def bitfield RB <20:16>;
104
105// Memory format
106def signed bitfield MEMDISP <15: 0>; // displacement
107def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
108
109// Memory-format jumps
110def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
111def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
112
113// Branch format
114def signed bitfield BRDISP <20: 0>; // displacement
115
116// Integer operate format(s>;
117def bitfield INTIMM <20:13>; // integer immediate (literal)
118def bitfield IMM <12:12>; // immediate flag
119def bitfield INTFUNC <11: 5>; // function code
120def bitfield RC < 4: 0>; // dest reg
121
122// Floating-point operate format
123def bitfield FA <25:21>;
124def bitfield FB <20:16>;
125def bitfield FP_FULLFUNC <15: 5>; // complete function code
126 def bitfield FP_TRAPMODE <15:13>; // trapping mode
127 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
128 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
129 def bitfield FP_SRCTYPE <10: 9>; // source reg type
130 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
131 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
132def bitfield FC < 4: 0>; // dest reg
133
134// PALcode format
135def bitfield PALFUNC <25: 0>; // function code
136
137// EV5 PAL instructions:
138// HW_LD/HW_ST
139def bitfield HW_LDST_PHYS <15>; // address is physical
140def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
141def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
142def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
143def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
144def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
145def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
146def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
147
148// HW_REI
149def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
150def bitfield HW_REI_MBZ <13: 0>; // must be zero
151
152// HW_MTPR/MW_MFPR
153def bitfield HW_IPR_IDX <15:0>; // IPR index
154
155// M5 instructions
156def bitfield M5FUNC <7:0>;
157
158def operand_types {{
159 'sb' : ('signed int', 8),
160 'ub' : ('unsigned int', 8),
161 'sw' : ('signed int', 16),
162 'uw' : ('unsigned int', 16),
163 'sl' : ('signed int', 32),
164 'ul' : ('unsigned int', 32),
165 'sq' : ('signed int', 64),
166 'uq' : ('unsigned int', 64),
167 'sf' : ('float', 32),
168 'df' : ('float', 64)
169}};
170
171def operands {{
172 # Int regs default to unsigned, but code should not count on this.
173 # For clarity, descriptions that depend on unsigned behavior should
174 # explicitly specify '.uq'.
175 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
176 'IsInteger', 1),
177 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
178 'IsInteger', 2),
179 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
180 'IsInteger', 3),
181 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
182 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
183 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
184 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
185 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
186 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
187 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
188 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
189 # The next two are hacks for non-full-system call-pal emulation
190 'R0': ('IntReg', 'uq', '0', None, 1),
191 'R16': ('IntReg', 'uq', '16', None, 1),
192 'R17': ('IntReg', 'uq', '17', None, 1),
193 'R18': ('IntReg', 'uq', '18', None, 1)
194}};
195
196////////////////////////////////////////////////////////////////////
197//
198// Basic instruction classes/templates/formats etc.
199//
200
201output header {{
202// uncomment the following to get SimpleScalar-compatible disassembly
203// (useful for diffing output traces).
204// #define SS_COMPATIBLE_DISASSEMBLY
205
206 /**
207 * Base class for all Alpha static instructions.
208 */
209 class AlphaStaticInst : public StaticInst
210 {
211 protected:
212
213 /// Make AlphaISA register dependence tags directly visible in
214 /// this class and derived classes. Maybe these should really
215 /// live here and not in the AlphaISA namespace.
216 enum DependenceTags {
217 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
218 };
219
220 /// Constructor.
221 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
222 OpClass __opClass)
223 : StaticInst(mnem, _machInst, __opClass)
224 {
225 }
226
227 /// Print a register name for disassembly given the unique
228 /// dependence tag number (FP or int).
229 void printReg(std::ostream &os, int reg) const;
230
231 std::string
232 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
233 };
234}};
235
236output decoder {{
237 void
238 AlphaStaticInst::printReg(std::ostream &os, int reg) const
239 {
240 if (reg < FP_Base_DepTag) {
241 ccprintf(os, "r%d", reg);
242 }
243 else {
244 ccprintf(os, "f%d", reg - FP_Base_DepTag);
245 }
246 }
247
248 std::string
249 AlphaStaticInst::generateDisassembly(Addr pc,
250 const SymbolTable *symtab) const
251 {
252 std::stringstream ss;
253
254 ccprintf(ss, "%-10s ", mnemonic);
255
256 // just print the first two source regs... if there's
257 // a third one, it's a read-modify-write dest (Rc),
258 // e.g. for CMOVxx
259 if (_numSrcRegs > 0) {
260 printReg(ss, _srcRegIdx[0]);
261 }
262 if (_numSrcRegs > 1) {
263 ss << ",";
264 printReg(ss, _srcRegIdx[1]);
265 }
266
267 // just print the first dest... if there's a second one,
268 // it's generally implicit
269 if (_numDestRegs > 0) {
270 if (_numSrcRegs > 0)
271 ss << ",";
272 printReg(ss, _destRegIdx[0]);
273 }
274
275 return ss.str();
276 }
277}};
278
279// Declarations for execute() methods.
280def template BasicExecDeclare {{
281 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
282}};
283
284// Basic instruction class declaration template.
285def template BasicDeclare {{
286 /**
287 * Static instruction class for "%(mnemonic)s".
288 */
289 class %(class_name)s : public %(base_class)s
290 {
291 public:
292 /// Constructor.
293 %(class_name)s(ExtMachInst machInst);
294
295 %(BasicExecDeclare)s
296 };
297}};
298
299// Basic instruction class constructor template.
300def template BasicConstructor {{
301 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
302 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
303 {
304 %(constructor)s;
305 }
306}};
307
308// Basic instruction class execute method template.
309def template BasicExecute {{
310 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
311 Trace::InstRecord *traceData) const
312 {
313 Fault fault = NoFault;
314
315 %(fp_enable_check)s;
316 %(op_decl)s;
317 %(op_rd)s;
318 %(code)s;
319
320 if (fault == NoFault) {
321 %(op_wb)s;
322 }
323
324 return fault;
325 }
326}};
327
328// Basic decode template.
329def template BasicDecode {{
330 return new %(class_name)s(machInst);
331}};
332
333// Basic decode template, passing mnemonic in as string arg to constructor.
334def template BasicDecodeWithMnemonic {{
335 return new %(class_name)s("%(mnemonic)s", machInst);
336}};
337
338// The most basic instruction format... used only for a few misc. insts
339def format BasicOperate(code, *flags) {{
340 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
341 header_output = BasicDeclare.subst(iop)
342 decoder_output = BasicConstructor.subst(iop)
343 decode_block = BasicDecode.subst(iop)
344 exec_output = BasicExecute.subst(iop)
345}};
346
347
348
349////////////////////////////////////////////////////////////////////
350//
351// Nop
352//
353
354output header {{
355 /**
356 * Static instruction class for no-ops. This is a leaf class.
357 */
358 class Nop : public AlphaStaticInst
359 {
360 /// Disassembly of original instruction.
361 const std::string originalDisassembly;
362
363 public:
364 /// Constructor
365 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
366 : AlphaStaticInst("nop", _machInst, No_OpClass),
367 originalDisassembly(_originalDisassembly)
368 {
369 flags[IsNop] = true;
370 }
371
372 ~Nop() { }
373
374 std::string
375 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
376
377 %(BasicExecDeclare)s
378 };
379
380 /// Helper function for decoding nops. Substitute Nop object
381 /// for original inst passed in as arg (and delete latter).
382 static inline
383 AlphaStaticInst *
384 makeNop(AlphaStaticInst *inst)
385 {
386 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
387 delete inst;
388 return nop;
389 }
390}};
391
392output decoder {{
393 std::string Nop::generateDisassembly(Addr pc,
394 const SymbolTable *symtab) const
395 {
396#ifdef SS_COMPATIBLE_DISASSEMBLY
397 return originalDisassembly;
398#else
399 return csprintf("%-10s (%s)", "nop", originalDisassembly);
400#endif
401 }
402}};
403
404output exec {{
405 Fault
406 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
407 {
408 return NoFault;
409 }
410}};
411
412// integer & FP operate instructions use Rc as dest, so check for
413// Rc == 31 to detect nops
414def template OperateNopCheckDecode {{
415 {
416 AlphaStaticInst *i = new %(class_name)s(machInst);
417 if (RC == 31) {
418 i = makeNop(i);
419 }
420 return i;
421 }
422}};
423
424// Like BasicOperate format, but generates NOP if RC/FC == 31
425def format BasicOperateWithNopCheck(code, *opt_args) {{
426 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
427 header_output = BasicDeclare.subst(iop)
428 decoder_output = BasicConstructor.subst(iop)
429 decode_block = OperateNopCheckDecode.subst(iop)
430 exec_output = BasicExecute.subst(iop)
431}};
432
433// Integer instruction templates, formats, etc.
434##include "int.isa"
435
436// Floating-point instruction templates, formats, etc.
437##include "fp.isa"
438
439// Memory instruction templates, formats, etc.
440##include "mem.isa"
441
442// Branch/jump instruction templates, formats, etc.
443##include "branch.isa"
444
445// PAL instruction templates, formats, etc.
446##include "pal.isa"
447
448// Opcdec fault instruction templates, formats, etc.
449##include "opcdec.isa"
450
451// Unimplemented instruction templates, formats, etc.
452##include "unimp.isa"
453
454// Unknown instruction templates, formats, etc.
455##include "unknown.isa"
456
457// Execution utility functions
458##include "util.isa"
459
460// The actual decoder
461##include "decoder.isa"
| 76#include "base/fenv.hh"
77#include "config/ss_compatible_fp.hh"
78#include "cpu/base.hh"
79#include "cpu/exetrace.hh"
80#include "mem/packet.hh"
81#include "mem/packet_access.hh"
82#include "sim/sim_exit.hh"
83
84using namespace AlphaISA;
85}};
86
87////////////////////////////////////////////////////////////////////
88//
89// Namespace statement. Everything below this line will be in the
90// AlphaISAInst namespace.
91//
92
93
94namespace AlphaISA;
95
96////////////////////////////////////////////////////////////////////
97//
98// Bitfield definitions.
99//
100
101// Universal (format-independent) fields
102def bitfield PALMODE <32:32>;
103def bitfield OPCODE <31:26>;
104def bitfield RA <25:21>;
105def bitfield RB <20:16>;
106
107// Memory format
108def signed bitfield MEMDISP <15: 0>; // displacement
109def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
110
111// Memory-format jumps
112def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
113def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
114
115// Branch format
116def signed bitfield BRDISP <20: 0>; // displacement
117
118// Integer operate format(s>;
119def bitfield INTIMM <20:13>; // integer immediate (literal)
120def bitfield IMM <12:12>; // immediate flag
121def bitfield INTFUNC <11: 5>; // function code
122def bitfield RC < 4: 0>; // dest reg
123
124// Floating-point operate format
125def bitfield FA <25:21>;
126def bitfield FB <20:16>;
127def bitfield FP_FULLFUNC <15: 5>; // complete function code
128 def bitfield FP_TRAPMODE <15:13>; // trapping mode
129 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
130 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
131 def bitfield FP_SRCTYPE <10: 9>; // source reg type
132 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
133 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
134def bitfield FC < 4: 0>; // dest reg
135
136// PALcode format
137def bitfield PALFUNC <25: 0>; // function code
138
139// EV5 PAL instructions:
140// HW_LD/HW_ST
141def bitfield HW_LDST_PHYS <15>; // address is physical
142def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
143def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
144def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
145def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
146def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
147def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
148def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
149
150// HW_REI
151def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
152def bitfield HW_REI_MBZ <13: 0>; // must be zero
153
154// HW_MTPR/MW_MFPR
155def bitfield HW_IPR_IDX <15:0>; // IPR index
156
157// M5 instructions
158def bitfield M5FUNC <7:0>;
159
160def operand_types {{
161 'sb' : ('signed int', 8),
162 'ub' : ('unsigned int', 8),
163 'sw' : ('signed int', 16),
164 'uw' : ('unsigned int', 16),
165 'sl' : ('signed int', 32),
166 'ul' : ('unsigned int', 32),
167 'sq' : ('signed int', 64),
168 'uq' : ('unsigned int', 64),
169 'sf' : ('float', 32),
170 'df' : ('float', 64)
171}};
172
173def operands {{
174 # Int regs default to unsigned, but code should not count on this.
175 # For clarity, descriptions that depend on unsigned behavior should
176 # explicitly specify '.uq'.
177 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
178 'IsInteger', 1),
179 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
180 'IsInteger', 2),
181 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
182 'IsInteger', 3),
183 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
184 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
185 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
186 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
187 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
188 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
189 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
190 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
191 # The next two are hacks for non-full-system call-pal emulation
192 'R0': ('IntReg', 'uq', '0', None, 1),
193 'R16': ('IntReg', 'uq', '16', None, 1),
194 'R17': ('IntReg', 'uq', '17', None, 1),
195 'R18': ('IntReg', 'uq', '18', None, 1)
196}};
197
198////////////////////////////////////////////////////////////////////
199//
200// Basic instruction classes/templates/formats etc.
201//
202
203output header {{
204// uncomment the following to get SimpleScalar-compatible disassembly
205// (useful for diffing output traces).
206// #define SS_COMPATIBLE_DISASSEMBLY
207
208 /**
209 * Base class for all Alpha static instructions.
210 */
211 class AlphaStaticInst : public StaticInst
212 {
213 protected:
214
215 /// Make AlphaISA register dependence tags directly visible in
216 /// this class and derived classes. Maybe these should really
217 /// live here and not in the AlphaISA namespace.
218 enum DependenceTags {
219 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
220 };
221
222 /// Constructor.
223 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
224 OpClass __opClass)
225 : StaticInst(mnem, _machInst, __opClass)
226 {
227 }
228
229 /// Print a register name for disassembly given the unique
230 /// dependence tag number (FP or int).
231 void printReg(std::ostream &os, int reg) const;
232
233 std::string
234 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
235 };
236}};
237
238output decoder {{
239 void
240 AlphaStaticInst::printReg(std::ostream &os, int reg) const
241 {
242 if (reg < FP_Base_DepTag) {
243 ccprintf(os, "r%d", reg);
244 }
245 else {
246 ccprintf(os, "f%d", reg - FP_Base_DepTag);
247 }
248 }
249
250 std::string
251 AlphaStaticInst::generateDisassembly(Addr pc,
252 const SymbolTable *symtab) const
253 {
254 std::stringstream ss;
255
256 ccprintf(ss, "%-10s ", mnemonic);
257
258 // just print the first two source regs... if there's
259 // a third one, it's a read-modify-write dest (Rc),
260 // e.g. for CMOVxx
261 if (_numSrcRegs > 0) {
262 printReg(ss, _srcRegIdx[0]);
263 }
264 if (_numSrcRegs > 1) {
265 ss << ",";
266 printReg(ss, _srcRegIdx[1]);
267 }
268
269 // just print the first dest... if there's a second one,
270 // it's generally implicit
271 if (_numDestRegs > 0) {
272 if (_numSrcRegs > 0)
273 ss << ",";
274 printReg(ss, _destRegIdx[0]);
275 }
276
277 return ss.str();
278 }
279}};
280
281// Declarations for execute() methods.
282def template BasicExecDeclare {{
283 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
284}};
285
286// Basic instruction class declaration template.
287def template BasicDeclare {{
288 /**
289 * Static instruction class for "%(mnemonic)s".
290 */
291 class %(class_name)s : public %(base_class)s
292 {
293 public:
294 /// Constructor.
295 %(class_name)s(ExtMachInst machInst);
296
297 %(BasicExecDeclare)s
298 };
299}};
300
301// Basic instruction class constructor template.
302def template BasicConstructor {{
303 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
305 {
306 %(constructor)s;
307 }
308}};
309
310// Basic instruction class execute method template.
311def template BasicExecute {{
312 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
313 Trace::InstRecord *traceData) const
314 {
315 Fault fault = NoFault;
316
317 %(fp_enable_check)s;
318 %(op_decl)s;
319 %(op_rd)s;
320 %(code)s;
321
322 if (fault == NoFault) {
323 %(op_wb)s;
324 }
325
326 return fault;
327 }
328}};
329
330// Basic decode template.
331def template BasicDecode {{
332 return new %(class_name)s(machInst);
333}};
334
335// Basic decode template, passing mnemonic in as string arg to constructor.
336def template BasicDecodeWithMnemonic {{
337 return new %(class_name)s("%(mnemonic)s", machInst);
338}};
339
340// The most basic instruction format... used only for a few misc. insts
341def format BasicOperate(code, *flags) {{
342 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
343 header_output = BasicDeclare.subst(iop)
344 decoder_output = BasicConstructor.subst(iop)
345 decode_block = BasicDecode.subst(iop)
346 exec_output = BasicExecute.subst(iop)
347}};
348
349
350
351////////////////////////////////////////////////////////////////////
352//
353// Nop
354//
355
356output header {{
357 /**
358 * Static instruction class for no-ops. This is a leaf class.
359 */
360 class Nop : public AlphaStaticInst
361 {
362 /// Disassembly of original instruction.
363 const std::string originalDisassembly;
364
365 public:
366 /// Constructor
367 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
368 : AlphaStaticInst("nop", _machInst, No_OpClass),
369 originalDisassembly(_originalDisassembly)
370 {
371 flags[IsNop] = true;
372 }
373
374 ~Nop() { }
375
376 std::string
377 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
378
379 %(BasicExecDeclare)s
380 };
381
382 /// Helper function for decoding nops. Substitute Nop object
383 /// for original inst passed in as arg (and delete latter).
384 static inline
385 AlphaStaticInst *
386 makeNop(AlphaStaticInst *inst)
387 {
388 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
389 delete inst;
390 return nop;
391 }
392}};
393
394output decoder {{
395 std::string Nop::generateDisassembly(Addr pc,
396 const SymbolTable *symtab) const
397 {
398#ifdef SS_COMPATIBLE_DISASSEMBLY
399 return originalDisassembly;
400#else
401 return csprintf("%-10s (%s)", "nop", originalDisassembly);
402#endif
403 }
404}};
405
406output exec {{
407 Fault
408 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
409 {
410 return NoFault;
411 }
412}};
413
414// integer & FP operate instructions use Rc as dest, so check for
415// Rc == 31 to detect nops
416def template OperateNopCheckDecode {{
417 {
418 AlphaStaticInst *i = new %(class_name)s(machInst);
419 if (RC == 31) {
420 i = makeNop(i);
421 }
422 return i;
423 }
424}};
425
426// Like BasicOperate format, but generates NOP if RC/FC == 31
427def format BasicOperateWithNopCheck(code, *opt_args) {{
428 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
429 header_output = BasicDeclare.subst(iop)
430 decoder_output = BasicConstructor.subst(iop)
431 decode_block = OperateNopCheckDecode.subst(iop)
432 exec_output = BasicExecute.subst(iop)
433}};
434
435// Integer instruction templates, formats, etc.
436##include "int.isa"
437
438// Floating-point instruction templates, formats, etc.
439##include "fp.isa"
440
441// Memory instruction templates, formats, etc.
442##include "mem.isa"
443
444// Branch/jump instruction templates, formats, etc.
445##include "branch.isa"
446
447// PAL instruction templates, formats, etc.
448##include "pal.isa"
449
450// Opcdec fault instruction templates, formats, etc.
451##include "opcdec.isa"
452
453// Unimplemented instruction templates, formats, etc.
454##include "unimp.isa"
455
456// Unknown instruction templates, formats, etc.
457##include "unknown.isa"
458
459// Execution utility functions
460##include "util.isa"
461
462// The actual decoder
463##include "decoder.isa"
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