1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <iomanip>
45#include <iostream>
46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh" // some constructors use MemReq flags
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <iomanip>
45#include <iostream>
46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh" // some constructors use MemReq flags
|
| 54#include "sim/byteswap.hh"
55
|
54}};
55
56output decoder {{
57#include <cmath>
58
59#include "arch/alpha/decoder.hh"
60#include "arch/alpha/registers.hh"
61#include "arch/alpha/regredir.hh"
| 56}};
57
58output decoder {{
59#include <cmath>
60
61#include "arch/alpha/decoder.hh"
62#include "arch/alpha/registers.hh"
63#include "arch/alpha/regredir.hh"
|
62#include "base/loader/symtab.hh"
| |
63#include "base/cprintf.hh"
64#include "base/fenv.hh"
| 64#include "base/cprintf.hh"
65#include "base/fenv.hh"
|
| 66#include "base/loader/symtab.hh"
|
65#include "config/ss_compatible_fp.hh"
66#include "cpu/thread_context.hh" // for Jump::branchTarget()
67#include "mem/packet.hh"
68#include "sim/full_system.hh"
69
70using namespace AlphaISA;
71}};
72
73output exec {{
74#include <cmath>
75
76#include "arch/alpha/decoder.hh"
77#include "arch/alpha/registers.hh"
78#include "arch/alpha/regredir.hh"
79#include "arch/generic/memhelpers.hh"
80#include "base/cp_annotate.hh"
81#include "base/fenv.hh"
82#include "config/ss_compatible_fp.hh"
83#include "cpu/base.hh"
84#include "cpu/exetrace.hh"
85#include "mem/packet.hh"
86#include "mem/packet_access.hh"
87#include "sim/full_system.hh"
88#include "sim/pseudo_inst.hh"
89#include "sim/sim_exit.hh"
90
91using namespace AlphaISA;
92}};
93
94////////////////////////////////////////////////////////////////////
95//
96// Namespace statement. Everything below this line will be in the
97// AlphaISAInst namespace.
98//
99
100
101namespace AlphaISA;
102
103////////////////////////////////////////////////////////////////////
104//
105// Bitfield definitions.
106//
107
108// Universal (format-independent) fields
109def bitfield PALMODE <32:32>;
110def bitfield OPCODE <31:26>;
111def bitfield RA <25:21>;
112def bitfield RB <20:16>;
113
114// Memory format
115def signed bitfield MEMDISP <15: 0>; // displacement
116def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
117
118// Memory-format jumps
119def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
120def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
121
122// Branch format
123def signed bitfield BRDISP <20: 0>; // displacement
124
125// Integer operate format(s>;
126def bitfield INTIMM <20:13>; // integer immediate (literal)
127def bitfield IMM <12:12>; // immediate flag
128def bitfield INTFUNC <11: 5>; // function code
129def bitfield RC < 4: 0>; // dest reg
130
131// Floating-point operate format
132def bitfield FA <25:21>;
133def bitfield FB <20:16>;
134def bitfield FP_FULLFUNC <15: 5>; // complete function code
135 def bitfield FP_TRAPMODE <15:13>; // trapping mode
136 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
137 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
138 def bitfield FP_SRCTYPE <10: 9>; // source reg type
139 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
140 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
141def bitfield FC < 4: 0>; // dest reg
142
143// PALcode format
144def bitfield PALFUNC <25: 0>; // function code
145
146// EV5 PAL instructions:
147// HW_LD/HW_ST
148def bitfield HW_LDST_PHYS <15>; // address is physical
149def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
150def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
151def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
152def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
153def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
154def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
155def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
156
157// HW_REI
158def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
159def bitfield HW_REI_MBZ <13: 0>; // must be zero
160
161// HW_MTPR/MW_MFPR
162def bitfield HW_IPR_IDX <15:0>; // IPR index
163
164// M5 instructions
165def bitfield M5FUNC <7:0>;
166
167def operand_types {{
168 'sb' : 'int8_t',
169 'ub' : 'uint8_t',
170 'sw' : 'int16_t',
171 'uw' : 'uint16_t',
172 'sl' : 'int32_t',
173 'ul' : 'uint32_t',
174 'sq' : 'int64_t',
175 'uq' : 'uint64_t',
176 'sf' : 'float',
177 'df' : 'double'
178}};
179
180def operands {{
181 # Int regs default to unsigned, but code should not count on this.
182 # For clarity, descriptions that depend on unsigned behavior should
183 # explicitly specify '_uq'.
184 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
185 'IsInteger', 1),
186 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
187 'IsInteger', 2),
188 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
189 'IsInteger', 3),
190 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
191 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
192 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
193 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
194 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
195 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
196 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
197 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
198 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
199 # The next two are hacks for non-full-system call-pal emulation
200 'R0': ('IntReg', 'uq', '0', None, 1),
201 'R16': ('IntReg', 'uq', '16', None, 1),
202 'R17': ('IntReg', 'uq', '17', None, 1),
203 'R18': ('IntReg', 'uq', '18', None, 1)
204}};
205
206////////////////////////////////////////////////////////////////////
207//
208// Basic instruction classes/templates/formats etc.
209//
210
211output header {{
212// uncomment the following to get SimpleScalar-compatible disassembly
213// (useful for diffing output traces).
214// #define SS_COMPATIBLE_DISASSEMBLY
215
216 /**
217 * Base class for all Alpha static instructions.
218 */
219 class AlphaStaticInst : public StaticInst
220 {
221 protected:
| 67#include "config/ss_compatible_fp.hh"
68#include "cpu/thread_context.hh" // for Jump::branchTarget()
69#include "mem/packet.hh"
70#include "sim/full_system.hh"
71
72using namespace AlphaISA;
73}};
74
75output exec {{
76#include <cmath>
77
78#include "arch/alpha/decoder.hh"
79#include "arch/alpha/registers.hh"
80#include "arch/alpha/regredir.hh"
81#include "arch/generic/memhelpers.hh"
82#include "base/cp_annotate.hh"
83#include "base/fenv.hh"
84#include "config/ss_compatible_fp.hh"
85#include "cpu/base.hh"
86#include "cpu/exetrace.hh"
87#include "mem/packet.hh"
88#include "mem/packet_access.hh"
89#include "sim/full_system.hh"
90#include "sim/pseudo_inst.hh"
91#include "sim/sim_exit.hh"
92
93using namespace AlphaISA;
94}};
95
96////////////////////////////////////////////////////////////////////
97//
98// Namespace statement. Everything below this line will be in the
99// AlphaISAInst namespace.
100//
101
102
103namespace AlphaISA;
104
105////////////////////////////////////////////////////////////////////
106//
107// Bitfield definitions.
108//
109
110// Universal (format-independent) fields
111def bitfield PALMODE <32:32>;
112def bitfield OPCODE <31:26>;
113def bitfield RA <25:21>;
114def bitfield RB <20:16>;
115
116// Memory format
117def signed bitfield MEMDISP <15: 0>; // displacement
118def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
119
120// Memory-format jumps
121def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
122def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
123
124// Branch format
125def signed bitfield BRDISP <20: 0>; // displacement
126
127// Integer operate format(s>;
128def bitfield INTIMM <20:13>; // integer immediate (literal)
129def bitfield IMM <12:12>; // immediate flag
130def bitfield INTFUNC <11: 5>; // function code
131def bitfield RC < 4: 0>; // dest reg
132
133// Floating-point operate format
134def bitfield FA <25:21>;
135def bitfield FB <20:16>;
136def bitfield FP_FULLFUNC <15: 5>; // complete function code
137 def bitfield FP_TRAPMODE <15:13>; // trapping mode
138 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
139 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
140 def bitfield FP_SRCTYPE <10: 9>; // source reg type
141 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
142 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
143def bitfield FC < 4: 0>; // dest reg
144
145// PALcode format
146def bitfield PALFUNC <25: 0>; // function code
147
148// EV5 PAL instructions:
149// HW_LD/HW_ST
150def bitfield HW_LDST_PHYS <15>; // address is physical
151def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
152def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
153def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
154def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
155def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
156def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
157def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
158
159// HW_REI
160def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
161def bitfield HW_REI_MBZ <13: 0>; // must be zero
162
163// HW_MTPR/MW_MFPR
164def bitfield HW_IPR_IDX <15:0>; // IPR index
165
166// M5 instructions
167def bitfield M5FUNC <7:0>;
168
169def operand_types {{
170 'sb' : 'int8_t',
171 'ub' : 'uint8_t',
172 'sw' : 'int16_t',
173 'uw' : 'uint16_t',
174 'sl' : 'int32_t',
175 'ul' : 'uint32_t',
176 'sq' : 'int64_t',
177 'uq' : 'uint64_t',
178 'sf' : 'float',
179 'df' : 'double'
180}};
181
182def operands {{
183 # Int regs default to unsigned, but code should not count on this.
184 # For clarity, descriptions that depend on unsigned behavior should
185 # explicitly specify '_uq'.
186 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
187 'IsInteger', 1),
188 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
189 'IsInteger', 2),
190 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
191 'IsInteger', 3),
192 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
193 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
194 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
195 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
196 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
197 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
198 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
199 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
200 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
201 # The next two are hacks for non-full-system call-pal emulation
202 'R0': ('IntReg', 'uq', '0', None, 1),
203 'R16': ('IntReg', 'uq', '16', None, 1),
204 'R17': ('IntReg', 'uq', '17', None, 1),
205 'R18': ('IntReg', 'uq', '18', None, 1)
206}};
207
208////////////////////////////////////////////////////////////////////
209//
210// Basic instruction classes/templates/formats etc.
211//
212
213output header {{
214// uncomment the following to get SimpleScalar-compatible disassembly
215// (useful for diffing output traces).
216// #define SS_COMPATIBLE_DISASSEMBLY
217
218 /**
219 * Base class for all Alpha static instructions.
220 */
221 class AlphaStaticInst : public StaticInst
222 {
223 protected:
|
222
| |
223 /// Constructor.
224 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
225 OpClass __opClass)
226 : StaticInst(mnem, _machInst, __opClass)
227 {
228 }
229
230 /// Print a register name for disassembly given the unique
231 /// dependence tag number (FP or int).
232 void printReg(std::ostream &os, RegId reg) const;
233
234 std::string
235 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
236
237 void
238 advancePC(AlphaISA::PCState &pcState) const
239 {
240 pcState.advance();
241 }
| 224 /// Constructor.
225 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
226 OpClass __opClass)
227 : StaticInst(mnem, _machInst, __opClass)
228 {
229 }
230
231 /// Print a register name for disassembly given the unique
232 /// dependence tag number (FP or int).
233 void printReg(std::ostream &os, RegId reg) const;
234
235 std::string
236 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
237
238 void
239 advancePC(AlphaISA::PCState &pcState) const
240 {
241 pcState.advance();
242 }
|
| 243
244 public:
245 size_t
246 asBytes(void *buf, size_t max_size) override
247 {
248 return simpleAsBytes(buf, max_size, machInst);
249 }
|
242 };
243}};
244
245output decoder {{
246 void
247 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
248 {
249 if (reg.isIntReg()) {
250 ccprintf(os, "r%d", reg.index());
251 }
252 else {
253 ccprintf(os, "f%d", reg.index());
254 }
255 }
256
257 std::string
258 AlphaStaticInst::generateDisassembly(Addr pc,
259 const SymbolTable *symtab) const
260 {
261 std::stringstream ss;
262
263 ccprintf(ss, "%-10s ", mnemonic);
264
265 // just print the first two source regs... if there's
266 // a third one, it's a read-modify-write dest (Rc),
267 // e.g. for CMOVxx
268 if (_numSrcRegs > 0) {
269 printReg(ss, _srcRegIdx[0]);
270 }
271 if (_numSrcRegs > 1) {
272 ss << ",";
273 printReg(ss, _srcRegIdx[1]);
274 }
275
276 // just print the first dest... if there's a second one,
277 // it's generally implicit
278 if (_numDestRegs > 0) {
279 if (_numSrcRegs > 0)
280 ss << ",";
281 printReg(ss, _destRegIdx[0]);
282 }
283
284 return ss.str();
285 }
286}};
287
288// Basic instruction class declaration template.
289def template BasicDeclare {{
290 /**
291 * Static instruction class for "%(mnemonic)s".
292 */
293 class %(class_name)s : public %(base_class)s
294 {
295 public:
296 /// Constructor.
297 %(class_name)s(ExtMachInst machInst);
298
299 Fault execute(ExecContext *, Trace::InstRecord *) const;
300 };
301}};
302
303// Basic instruction class constructor template.
304def template BasicConstructor {{
305 %(class_name)s::%(class_name)s(ExtMachInst machInst)
306 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
307 {
308 %(constructor)s;
309 }
310}};
311
312// Basic instruction class execute method template.
313def template BasicExecute {{
314 Fault %(class_name)s::execute(ExecContext *xc,
315 Trace::InstRecord *traceData) const
316 {
317 Fault fault = NoFault;
318
319 %(fp_enable_check)s;
320 %(op_decl)s;
321 %(op_rd)s;
322 %(code)s;
323
324 if (fault == NoFault) {
325 %(op_wb)s;
326 }
327
328 return fault;
329 }
330}};
331
332// Basic decode template.
333def template BasicDecode {{
334 return new %(class_name)s(machInst);
335}};
336
337// Basic decode template, passing mnemonic in as string arg to constructor.
338def template BasicDecodeWithMnemonic {{
339 return new %(class_name)s("%(mnemonic)s", machInst);
340}};
341
342// The most basic instruction format... used only for a few misc. insts
343def format BasicOperate(code, *flags) {{
344 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
345 header_output = BasicDeclare.subst(iop)
346 decoder_output = BasicConstructor.subst(iop)
347 decode_block = BasicDecode.subst(iop)
348 exec_output = BasicExecute.subst(iop)
349}};
350
351
352
353////////////////////////////////////////////////////////////////////
354//
355// Nop
356//
357
358output header {{
359 /**
360 * Static instruction class for no-ops. This is a leaf class.
361 */
362 class Nop : public AlphaStaticInst
363 {
364 /// Disassembly of original instruction.
365 const std::string originalDisassembly;
366
367 public:
368 /// Constructor
369 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
370 : AlphaStaticInst("nop", _machInst, No_OpClass),
371 originalDisassembly(_originalDisassembly)
372 {
373 flags[IsNop] = true;
374 }
375
376 ~Nop() { }
377
378 std::string
379 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
380
381 Fault execute(ExecContext *, Trace::InstRecord *) const;
382 };
383
384 /// Helper function for decoding nops. Substitute Nop object
385 /// for original inst passed in as arg (and delete latter).
386 static inline
387 AlphaStaticInst *
388 makeNop(AlphaStaticInst *inst)
389 {
390 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
391 delete inst;
392 return nop;
393 }
394}};
395
396output decoder {{
397 std::string Nop::generateDisassembly(Addr pc,
398 const SymbolTable *symtab) const
399 {
400#ifdef SS_COMPATIBLE_DISASSEMBLY
401 return originalDisassembly;
402#else
403 return csprintf("%-10s (%s)", "nop", originalDisassembly);
404#endif
405 }
406}};
407
408output exec {{
409 Fault
410 Nop::execute(ExecContext *, Trace::InstRecord *) const
411 {
412 return NoFault;
413 }
414}};
415
416// integer & FP operate instructions use Rc as dest, so check for
417// Rc == 31 to detect nops
418def template OperateNopCheckDecode {{
419 {
420 AlphaStaticInst *i = new %(class_name)s(machInst);
421 if (RC == 31) {
422 i = makeNop(i);
423 }
424 return i;
425 }
426}};
427
428// Like BasicOperate format, but generates NOP if RC/FC == 31
429def format BasicOperateWithNopCheck(code, *opt_args) {{
430 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
431 header_output = BasicDeclare.subst(iop)
432 decoder_output = BasicConstructor.subst(iop)
433 decode_block = OperateNopCheckDecode.subst(iop)
434 exec_output = BasicExecute.subst(iop)
435}};
436
437// Integer instruction templates, formats, etc.
438##include "int.isa"
439
440// Floating-point instruction templates, formats, etc.
441##include "fp.isa"
442
443// Memory instruction templates, formats, etc.
444##include "mem.isa"
445
446// Branch/jump instruction templates, formats, etc.
447##include "branch.isa"
448
449// PAL instruction templates, formats, etc.
450##include "pal.isa"
451
452// Opcdec fault instruction templates, formats, etc.
453##include "opcdec.isa"
454
455// Unimplemented instruction templates, formats, etc.
456##include "unimp.isa"
457
458// Unknown instruction templates, formats, etc.
459##include "unknown.isa"
460
461// Execution utility functions
462##include "util.isa"
463
464// The actual decoder
465##include "decoder.isa"
| 250 };
251}};
252
253output decoder {{
254 void
255 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
256 {
257 if (reg.isIntReg()) {
258 ccprintf(os, "r%d", reg.index());
259 }
260 else {
261 ccprintf(os, "f%d", reg.index());
262 }
263 }
264
265 std::string
266 AlphaStaticInst::generateDisassembly(Addr pc,
267 const SymbolTable *symtab) const
268 {
269 std::stringstream ss;
270
271 ccprintf(ss, "%-10s ", mnemonic);
272
273 // just print the first two source regs... if there's
274 // a third one, it's a read-modify-write dest (Rc),
275 // e.g. for CMOVxx
276 if (_numSrcRegs > 0) {
277 printReg(ss, _srcRegIdx[0]);
278 }
279 if (_numSrcRegs > 1) {
280 ss << ",";
281 printReg(ss, _srcRegIdx[1]);
282 }
283
284 // just print the first dest... if there's a second one,
285 // it's generally implicit
286 if (_numDestRegs > 0) {
287 if (_numSrcRegs > 0)
288 ss << ",";
289 printReg(ss, _destRegIdx[0]);
290 }
291
292 return ss.str();
293 }
294}};
295
296// Basic instruction class declaration template.
297def template BasicDeclare {{
298 /**
299 * Static instruction class for "%(mnemonic)s".
300 */
301 class %(class_name)s : public %(base_class)s
302 {
303 public:
304 /// Constructor.
305 %(class_name)s(ExtMachInst machInst);
306
307 Fault execute(ExecContext *, Trace::InstRecord *) const;
308 };
309}};
310
311// Basic instruction class constructor template.
312def template BasicConstructor {{
313 %(class_name)s::%(class_name)s(ExtMachInst machInst)
314 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
315 {
316 %(constructor)s;
317 }
318}};
319
320// Basic instruction class execute method template.
321def template BasicExecute {{
322 Fault %(class_name)s::execute(ExecContext *xc,
323 Trace::InstRecord *traceData) const
324 {
325 Fault fault = NoFault;
326
327 %(fp_enable_check)s;
328 %(op_decl)s;
329 %(op_rd)s;
330 %(code)s;
331
332 if (fault == NoFault) {
333 %(op_wb)s;
334 }
335
336 return fault;
337 }
338}};
339
340// Basic decode template.
341def template BasicDecode {{
342 return new %(class_name)s(machInst);
343}};
344
345// Basic decode template, passing mnemonic in as string arg to constructor.
346def template BasicDecodeWithMnemonic {{
347 return new %(class_name)s("%(mnemonic)s", machInst);
348}};
349
350// The most basic instruction format... used only for a few misc. insts
351def format BasicOperate(code, *flags) {{
352 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
353 header_output = BasicDeclare.subst(iop)
354 decoder_output = BasicConstructor.subst(iop)
355 decode_block = BasicDecode.subst(iop)
356 exec_output = BasicExecute.subst(iop)
357}};
358
359
360
361////////////////////////////////////////////////////////////////////
362//
363// Nop
364//
365
366output header {{
367 /**
368 * Static instruction class for no-ops. This is a leaf class.
369 */
370 class Nop : public AlphaStaticInst
371 {
372 /// Disassembly of original instruction.
373 const std::string originalDisassembly;
374
375 public:
376 /// Constructor
377 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
378 : AlphaStaticInst("nop", _machInst, No_OpClass),
379 originalDisassembly(_originalDisassembly)
380 {
381 flags[IsNop] = true;
382 }
383
384 ~Nop() { }
385
386 std::string
387 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
388
389 Fault execute(ExecContext *, Trace::InstRecord *) const;
390 };
391
392 /// Helper function for decoding nops. Substitute Nop object
393 /// for original inst passed in as arg (and delete latter).
394 static inline
395 AlphaStaticInst *
396 makeNop(AlphaStaticInst *inst)
397 {
398 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
399 delete inst;
400 return nop;
401 }
402}};
403
404output decoder {{
405 std::string Nop::generateDisassembly(Addr pc,
406 const SymbolTable *symtab) const
407 {
408#ifdef SS_COMPATIBLE_DISASSEMBLY
409 return originalDisassembly;
410#else
411 return csprintf("%-10s (%s)", "nop", originalDisassembly);
412#endif
413 }
414}};
415
416output exec {{
417 Fault
418 Nop::execute(ExecContext *, Trace::InstRecord *) const
419 {
420 return NoFault;
421 }
422}};
423
424// integer & FP operate instructions use Rc as dest, so check for
425// Rc == 31 to detect nops
426def template OperateNopCheckDecode {{
427 {
428 AlphaStaticInst *i = new %(class_name)s(machInst);
429 if (RC == 31) {
430 i = makeNop(i);
431 }
432 return i;
433 }
434}};
435
436// Like BasicOperate format, but generates NOP if RC/FC == 31
437def format BasicOperateWithNopCheck(code, *opt_args) {{
438 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
439 header_output = BasicDeclare.subst(iop)
440 decoder_output = BasicConstructor.subst(iop)
441 decode_block = OperateNopCheckDecode.subst(iop)
442 exec_output = BasicExecute.subst(iop)
443}};
444
445// Integer instruction templates, formats, etc.
446##include "int.isa"
447
448// Floating-point instruction templates, formats, etc.
449##include "fp.isa"
450
451// Memory instruction templates, formats, etc.
452##include "mem.isa"
453
454// Branch/jump instruction templates, formats, etc.
455##include "branch.isa"
456
457// PAL instruction templates, formats, etc.
458##include "pal.isa"
459
460// Opcdec fault instruction templates, formats, etc.
461##include "opcdec.isa"
462
463// Unimplemented instruction templates, formats, etc.
464##include "unimp.isa"
465
466// Unknown instruction templates, formats, etc.
467##include "unknown.isa"
468
469// Execution utility functions
470##include "util.isa"
471
472// The actual decoder
473##include "decoder.isa"
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